Odysseas G. Koufopavlou

Affiliations:
  • University of Patras, Greece


According to our database1, Odysseas G. Koufopavlou authored at least 147 papers between 1990 and 2023.

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Bibliography

2023
PHOENI2X - A European Cyber Resilience Framework With Artificial-Intelligence-Assisted Orchestration, Automation and Response Capabilities for Business Continuity and Recovery, Incident Response, and Information Exchange.
CoRR, 2023

PHOENI2X - A European Cyber Resilience Framework With Artificial-Intelligence-Assisted Orchestration, Automation & Response Capabilities for Business Continuity and Recovery, Incident Response, and Information Exchange.
Proceedings of the IEEE International Conference on Cyber Security and Resilience, 2023

AMINet: An Industrial Honeynet for AMI Systems.
Proceedings of the IEEE International Conference on Big Data, 2023

2021
Machine Learning Attacks and Countermeasures on Hardware Binary Edwards Curve Scalar Multipliers.
J. Sens. Actuator Networks, 2021

Studying OpenCL-based Number Theoretic Transform for heterogeneous platforms.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020
Anomaly Detection Trusted Hardware Sensors for Critical Infrastructure Legacy Devices.
Sensors, 2020

Exploring the FPGA Implementations of the LBlock, Piccolo, Twine, and Klein Ciphers.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Profiling Dilithium Digital Signature Traces for Correlation Differential Side Channel Attacks.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

2019
Design and leakage assessment of side channel attack resistant binary edwards Elliptic Curve digital signature algorithm architectures.
Microprocess. Microsystems, 2019

Lightweight Efficient Simeck32/64 Crypto-Core Designs and Implementations, for IoT Security.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Revisiting Rowhammer Attacks in Embedded Systems.
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

2018
Trusted hardware sensors for anomaly detection in critical infrastructure systems.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

A flexible leakage trace collection setup for arbitrary cryptographic IP cores.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

2017
Hardware Security for Critical Infrastructures - The CIPSEC Project Approach.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A Design Strategy for Digit Serial Multiplier Based Binary Edwards Curve Scalar Multiplier Architectures.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Scalable playback rate control in P2P live streaming systems.
Peer-to-Peer Netw. Appl., 2016

Building softwarized mobile infrastructures with ForCES.
Proceedings of the 23rd International Conference on Telecommunications, 2016

2015
Software-Defined Networking (SDN): Layers and Architecture Terminology.
RFC, January, 2015

Comparing design approaches for elliptic curve point multiplication over <i>GF</i>(2<sup>k</sup>) with polynomial basis representation.
Microprocess. Microsystems, 2015

Towards a Network Abstraction Model for SDN.
J. Netw. Syst. Manag., 2015

Network Programmability With ForCES.
IEEE Commun. Surv. Tutorials, 2015

Designing efficient elliptic Curve Diffie-Hellman accelerators for embedded systems.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Affine Coordinate Binary Edwards Curve Scalar Multiplier with Side Channel Attack Resistance.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
Scalable control of bandwidth resources in P2P live streaming.
Proceedings of the 22nd Mediterranean Conference on Control and Automation, 2014

ForCES Applicability to SDN-Enhanced NFV.
Proceedings of the Third European Workshop on Software Defined Networks, 2014

Designing and Evaluating High Speed Elliptic Curve Point Multipliers.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2012
VLSI Design and Implementation of Homophonic Security System.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Protecting CRT RSA against Fault and Power Side Channel Attacks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Software-Defined Networking: Experimenting with the Control to Forwarding Plane Interface.
Proceedings of the European Workshop on Software Defined Networking, 2012

CRT RSA Hardware Architecture with Fault and Simple Power Attack Countermeasures.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Forwarding and Control Element Separation (ForCES) Implementation Experience.
RFC, September, 2011

LiquidStream - network dependent dynamic P2P live streaming.
Peer-to-Peer Netw. Appl., 2011

VITAL++, a new communication paradigm: embedding P2P technology in next generation networks.
IEEE Commun. Mag., 2011

Efficient CRT RSA with SCA Countermeasures.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Full custom low-power/high performance DDP-based Cobra-H64 cipher.
Comput. Electr. Eng., 2010

Teaching Introduction to Computing Through a Project-Based Collaborative Learning Approach.
Proceedings of the 14th Panhellenic Conference on Informatics, 2010

Adopting software engineering practices to network processor devices introducing the Domain Specific Modeling paradigm to the ForCES Framework.
Proceedings of the 6th International Conference on Network and Service Management, 2010

2009
Improved throughput bit-serial multiplier for GF(2<sup>m</sup>) fields.
Integr., 2009

Proposing a service-enabled semantic grid model.
Int. J. Auton. Adapt. Commun. Syst., 2009

Software and Hardware Issues in Smart Card Technology.
IEEE Commun. Surv. Tutorials, 2009

Low Area Elliptic Curve Arithmetic Unit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

On the architecture and the design of P2P live streaming system schedulers.
Proceedings of the International Conference on Ultra Modern Telecommunications, 2009

One Dimensional Systolic Inversion Architecture Based on Modified GF(2^k) Extended Euclidean Algorithm.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
Versatile multiplier architectures in GF(2<sup>k</sup>) fields using the Montgomery multiplication algorithm.
Integr., 2008

Towards a resource management and service deployment framework.
Int. J. Netw. Manag., 2008

Towards a service-enabled distributed router architecture.
IET Circuits Devices Syst., 2008

P2P-InfoReflect: Dynamic Locality-Aware and Multi-balanced Overlay for Network Dependent Applications and Services.
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications, 2008

Creating an Elliptic Curve arithmetic unit for use in elliptic curve cryptography.
Proceedings of 13th IEEE International Conference on Emerging Technologies and Factory Automation, 2008

A Hardware Implementation of CURUPIRA Block Cipher for Wireless Sensors.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
UMTS security: system architecture and hardware implementation.
Wirel. Commun. Mob. Comput., 2007

A Low Power Design for Sbox Cryptographic Primitive of Advanced Encryption Standard for Mobile End-Users.
J. Low Power Electron., 2007

Applying systolic multiplication-inversion architectures based on modified extended Euclidean algorithm for GF(2<sup>k</sup>) in elliptic curve cryptography.
Comput. Electr. Eng., 2007

Dynamic Deployment of Semantic-based Services in a Highly Distributed Environment.
Proceedings of the WEBIST 2007, 2007

AAA and mobile networks: security aspects and architectural efficiency.
Proceedings of the 3rd International Conference on Mobile Multimedia Communications, 2007

An optimal low-power/high performance DDP-based Cobra-H64 cipher.
Proceedings of the 3rd International Conference on Mobile Multimedia Communications, 2007

NASS-IMS bundled authentication study through core network concepts.
Proceedings of the 3rd International Conference on Mobile Multimedia Communications, 2007

An FPGA-based implementation of the Pomaranch stream cipher.
Proceedings of the 3rd International Conference on Mobile Multimedia Communications, 2007

Security Analysis of SIP Signalling during NASS-IMS bundled Authentication.
Proceedings of the Third International Conference on Networking and Services (ICNS 2007), 2007

Dynamic Service Deployment using an Ontologybased Description of Devices and Services.
Proceedings of the Third International Conference on Networking and Services (ICNS 2007), 2007

Optimization of the "FOCUS" Inband-FEC architecture for 10-Gbps SDH/SONET optical communication channels.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security.
J. Supercomput., 2006

Architectures and FPGA Implementations of the 64-Bit MISTY1 Block Cipher.
J. Circuits Syst. Comput., 2006

Applying Low Power Techniques in AES MixColumn/InvMixColumn Transformations.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A Systolic Inversion Architecture Based on Modified Extended Euclidean Algorithm for GF(2K) Fields.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Enabling Locality in a Balanced Peer-to-Peer Overlay.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2005
Implementation of the SHA-2 Hash Family Standard Using FPGAs.
J. Supercomput., 2005

High Speed Networking Security: Design and Implementation of Two New DDP-Based Ciphers.
Mob. Networks Appl., 2005

An Fpga Implementation of the Gprs Encryption Algorithm 3 (gea3).
J. Circuits Syst. Comput., 2005

Access Control in Networks Hierarchy: Implementation of Key Management Protocol.
Int. J. Netw. Secur., 2005

Pure DDP-Based Cipher: Architecture Analysis, Hardware Implementation Cost and Performance up to 6.5 Gbps.
Int. Arab J. Inf. Technol., 2005

On the hardware implementation of RIPEMD processor: Networking high speed hashing, up to 2Gbps.
Comput. Electr. Eng., 2005

Cryptography: Circuits and Systems Approach.
Proceedings of the Integrated Circuit and System Design, 2005

A Web Service- and ForCES-Based Programmable Router Architecture.
Proceedings of the Active and Programmable Networks, 2005

A Web-Services Based Architecture for Dynamic-Service Deployment.
Proceedings of the Active and Programmable Networks, 2005

A low-power and high-throughput implementation of the SHA-1 hash function.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A new RSA encryption architecture and hardware implementation based on optimized Montgomery multiplication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

VLSI design and implementation of reconfigurable cryptographic systems for symmetric encryption.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

A novel systolic GF(2k) field Multiplication-Inversion arithmetic unit.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

A systolic trinomial GF(2k) multiplier based on the Montgomery Multiplication Algorithm.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

Applying a Web-Service-Based Model to Dynamic Service-Deployment.
Proceedings of the 2005 International Conference on Computational Intelligence for Modelling Control and Automation (CIMCA 2005), 2005

Wireless Networks World and Security Algorithms.
Proceedings of the Handbook on Theoretical and Algorithmic Aspects of Sensor, 2005

2004
Efficient architecture and hardware implementation of the Whirlpool hash function.
IEEE Trans. Consumer Electron., 2004

Open Mobile Alliance (OMA) Security Layer: Architecture, Implementation and Performance Evaluation of the Integrity Unit.
New Gener. Comput., 2004

An Efficient Low-Swing Multithreshold-Voltage Low-Power Design Technique.
J. Circuits Syst. Comput., 2004

Multithreshold voltage low-swing/low-voltage techniques in logic gates.
Integr., 2004

Computer Network Security: Report from MMM-ACNS.
IEEE Secur. Priv., 2004

Configurable Hardware Implementations of Bulk Encryption Units for Wireless Communications.
Int. Arab J. Inf. Technol., 2004

In-band coding technique to promptly enhance SDH/SONET fiber-optic channels with FEC capabilities.
Eur. Trans. Telecommun., 2004

Low power high-speed multithreshold voltage CMOS bus architectures.
Comput. Electr. Eng., 2004

64-bit Block ciphers: hardware implementations and comparison analysis.
Comput. Electr. Eng., 2004

New class of the FPGA efficient cryptographic primitives.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Whirlpool hash function: architecture and VLSI implementation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

High-speed hardware implementations of the KASUMI block cipher.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

GF(2<sup>K</sup>) multipliers based on Montgomery Multiplication Algorithm.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Bulk encryption crypto-processor for smart cards: design and implementation.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

High performance cryptographic engine PANAMA: hardware implementation.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Comparison of the hardware architectures and FPGA implementations of stream ciphers.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003
Hardware Implementation of Bluetooth Security.
IEEE Pervasive Comput., 2003

An efficient reconfigurable multiplier architecture for Galois field GF(2<sup>m</sup>).
Microelectron. J., 2003

Networking Data Integrity: High Speed Architectures and Hardware Implementations.
Int. Arab J. Inf. Technol., 2003

Mobile Communications World: Security Implementations Aspects - A State of the Art.
Comput. Sci. J. Moldova, 2003

Data dependent rotations, a trustworthy approach for future encryption systems/ciphers: low cost and high performance.
Comput. Secur., 2003

Architectures and FPGA Implementations of the SCO(-1, -2, -3) Ciphers Family.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Encryption and Data Dependent Permutations: Implementation Cost and Performance Evaluation.
Proceedings of the Computer Network Security, 2003

On the hardware implementations of the SHA-2 (256, 384, 512) hash functions.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Area optimized architecture and VLSI implementation of RC5 encryption algorithm.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

An ultra high speed architecture for VLSI implementation of hash functions.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

VLSI implementation of the keyed-hash message authentication code for the wireless application protocol.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

An reconfigurable multiplier in GF(2<sup>m</sup>) for elliptic curve cryptosystem.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

VLSI implementations of the triple-DES block cipher.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

VLSI architecture and FPGA implementation of ICE encryption algorithm.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
Low-power Implementation of an Encryption/Decryption System with Asynchronous Techniques.
VLSI Design, 2002

Architectures and VLSI Implementations of the AES-Proposal Rijndael.
IEEE Trans. Computers, 2002

Random number generator architecture and VLSI implementation.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Hardware implementation of the SAFER+ encryption algorithm for the Bluetooth system.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Euclidean algorithm VLSI implementations.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

VLSI implementation of password (PIN) authentication unit.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

An efficient implementation of the digital signature algorithm.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001
Efficient Low Power/Low Swing Bus Design Architectures.
VLSI Design, 2001

Multi-level low swing voltage values for low power design applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Asynchronous low power VLSI implementation of the International Data Encryption Algorithm.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A reconfigurable linear feedback shift register (LFSR) for the Bluetooth system.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Multiple low swing voltage values for CPL, CVSL and domino logic families.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999
Power exploration of multimedia applications realized on embedded cores.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Low voltage swing gates for low power consumption.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

CMOS gate modeling based on equivalent inverter.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Multithreshold Voltage Technology for Low Power Bus Architecture.
Proceedings of the VLSI: Systems on a Chip, 1999

Efficient drivers, receivers and repeaters for low power CMOS bus architectures.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Low-swing/low power driver architecture.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Analytical modeling of short-circuit energy dissipation in submicron CMOS structures.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Data link control emulation: rapid prototyping for high-speed networks.
IEEE Netw., 1998

Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices.
IEEE J. Solid State Circuits, 1998

Analytical Model for the CMOS Short-Circuit Power Dissipation.
Integr. Comput. Aided Eng., 1998

Low-power domino logic multiplier using low-swing technique.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Switching Response Modeling of the CMOS Inverter for Sub-micron Devices.
Proceedings of the 1998 Design, 1998

1996
Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

A novel approach for reducing the switching activity in two-level logic circuits.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Accurate timing model for the CMOS inverter.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1994
On the Design of a Multigigabit IP Router.
J. High Speed Networks, 1994

A Comparison of Gigabit Router Architectures.
Proceedings of the High Performance Networking V, Proceedings of the IFIP TC6/WG6.4 Fifth International Conference on High Performance Networking, Grenoble, France, 27 June, 1994

1993
Space-Time Representation of Iterative Algorithms and The Design of Regular Processor Arrays.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

An ATM Communication Workstation.
Proceedings of the Broadband Islands: Towards Integration, 1993

1992
Image reconstruction on a special purpose array processor.
Image Vis. Comput., 1992

Analysis of TCP/IP for high performance parallel implementations.
Proceedings of the 17th Conference on Local Computer Networks, 1992

1991
Array processor for LS FIR system identification.
Microprocessing and Microprogramming, 1991

1990
A generator for a number format conversion IC.
Microprocessing and Microprogramming, 1990


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