Nuttorn Jangkrajarng
According to our database1,
Nuttorn Jangkrajarng
authored at least 12 papers
between 2003 and 2008.
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Bibliography
2008
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
2007
Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits.
Proceedings of the 25th International Conference on Computer Design, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 42nd Design Automation Conference, 2005
2004
Proceedings of the 41th Design Automation Conference, 2004
Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Hierarchical extraction and verification of symmetry constraints for analog layout automation.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Integr., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003