Nusrat Jahan Lisa

According to our database, Nusrat Jahan Lisa authored at least 13 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Integrating Multi-FPGA Acceleration to OpenMP Distributed Computing.

Pedro Henrique Di Francia Rosso, Lucian Petrica, Nusrat Jahan Lisa, Márcio Machado Pereira, Sandro Rigo, Hervé Yviquel, Vanderlei Bonato, Emilio Francesquini, Guido Araujo

Proceedings of the Advancing OpenMP for Future Accelerators, 2024

2021

COVID-19 Diagnosis from Chest X-ray Images Using Convolutional Neural Network(CNN) and InceptionV3.

Nazmus Shakib Shadin, Silvia Sanjana, Nusrat Jahan Lisa

Proceedings of the International Conference on Information Technology, 2021

2020

Adaptive Lightweight Compression Acceleration on Hybrid CPU-FPGA System.

Nusrat Jahan Lisa

PhD thesis, 2020

2019

High-Throughput BitPacking Compression.

Nusrat Jahan Lisa, Tuan Duy Anh Nguyen, Dirk Habich, Akash Kumar, Wolfgang Lehner

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018

Column Scan Acceleration in Hybrid CPU-FPGA Systems.

Nusrat Jahan Lisa, Annett Ungethüm, Dirk Habich, Wolfgang Lehner, Tuan D. A. Nguyen, Akash Kumar

Proceedings of the International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2018

Column Scan Optimization by Increasing Intra-Instruction Parallelism.

Nusrat Jahan Lisa, Annett Ungethüm, Dirk Habich, Tuan D. A. Nguyen, Akash Kumar, Wolfgang Lehner

Proceedings of the 7th International Conference on Data Science, 2018

FPGA vs. SIMD: Comparison for Main Memory-Based Fast Column Scan.

Nusrat Jahan Lisa, Annett Ungethüm, Dirk Habich, Wolfgang Lehner, Tuan Duy Anh Nguyen, Akash Kumar

Proceedings of the Data Management Technologies and Applications, 2018

2015

Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming.

Nusrat Jahan Lisa, Hafiz Md. Hasan Babu

Proceedings of the 28th International Conference on VLSI Design, 2015

Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing.

Nusrat Jahan Lisa, Hafiz Md. Hasan Babu

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

A compact representation of a quantum controlled ternary barrel shifter.

Nusrat Jahan Lisa, Hafiz Md. Hasan Babu

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A compact design of n-bit ripple carry adder circuit using QCA architecture.

Tania Sultana, Rajon Bardhan, Tangina Firoz Bithee, Zinia Tabassum, Nusrat Jahan Lisa

Proceedings of the 14th IEEE/ACIS International Conference on Computer and Information Science, 2015

2014

Minimization of a reversible quantum 2ⁿ-to-n BCD priority encoder.

Nusrat Jahan Lisa, Hafiz Md. Hasan Babu

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

A compact realization of an n-bit quantum carry skip adder circuit with optimal delay.

Nusrat Jahan Lisa, Hafiz Md. Hasan Babu

Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014