Nuno Paulino

Orcid: 0000-0001-5547-0323

According to our database1, Nuno Paulino authored at least 11 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study.
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024

A DSL and MLIR Dialect for Streaming and Vectorisation.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023
Challenges and Opportunities in C/C++ Source-To-Source Compilation (Invited Paper).
Proceedings of the 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2023

Enhancing NLoS RIS-Aided Localization with Optimization and Machine Learning.
Proceedings of the IEEE Globecom Workshops 2023, 2023

Retargeting Applications for Heterogeneous Systems with the Tribble Source-to-Source Framework.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022
Design and Experimental Evaluation of a Bluetooth 5.1 Antenna Array for Angle-of-Arrival Estimation.
Proceedings of the 13th International Symposium on Communication Systems, 2022

2021
FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example.
Proceedings of the International Conference on Field-Programmable Technology, 2021

On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators.
Proceedings of the International Conference on Field-Programmable Technology, 2021

Evaluating a Novel Bluetooth 5.1 AoA Approach for Low-Cost Indoor Vehicle Tracking via Simulation.
Proceedings of the Joint European Conference on Networks and Communications & 6G Summit, 2021

2020
Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2017
On Coding Techniques for Targeting FPGAs via OpenCL.
Proceedings of the Parallel Computing is Everywhere, 2017


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