Nuno Miguel Cardanha Paulino

According to our database, Nuno Miguel Cardanha Paulino authored at least 36 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Vision-Radio Experimental Infrastructure Architecture Towards 6G.

Filipe B. Teixeira, Manuel Ricardo, André Coelho, Hélder P. Oliveira, Paula Viana, Nuno Paulino, Helder Fontes, Paulo Marques, Rui Campos, Luís M. Pessoa

CoRR, 2024

Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study.

Miguel Henriques, João Bispo, Nuno Paulino

Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024

SpecRF-Posture: Exploring Specular Reflections for Human Posture Recognition.

Mariana Oliveira, Francisco M. Ribeiro, Nuno Paulino, Okan Yurduseven, Luís M. Pessoa

Proceedings of the IEEE International Mediterranean Conference on Communications and Networking, 2024

CONVERGE: A Vision-Radio Research Infrastructure Towards 6G and Beyond.

Filipe B. Teixeira, Manuel Ricardo, André Coelho, Hélder P. Oliveira, Paula Viana, Nuno Paulino, Helder Fontes, Paulo Marques, Rui Campos, Luís M. Pessoa

Proceedings of the Joint European Conference on Networks and Communications & 6G Summit, 2024

A Deep Learning Approach in RIS-based Indoor Localization.

Rafael A. Aguiar, Nuno Paulino, Luís M. Pessoa

Proceedings of the Joint European Conference on Networks and Communications & 6G Summit, 2024

A DSL and MLIR Dialect for Streaming and Vectorisation.

Manuel Cerqueira da Silva, Luís Miguel Sousa, Nuno Paulino, João Bispo

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023

Self-Localization via Circular Bluetooth 5.1 Antenna Array Receiver.

Nuno Paulino, Luís M. Pessoa

IEEE Access, 2023

Challenges and Opportunities in C/C++ Source-To-Source Compilation (Invited Paper).

João Bispo, Nuno Paulino, Luís Miguel Sousa

Proceedings of the 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2023

Enhancing NLoS RIS-Aided Localization with Optimization and Machine Learning.

Rafael A. Aguiar, Nuno Paulino, Luís M. Pessoa

Proceedings of the IEEE Globecom Workshops 2023, 2023

Retargeting Applications for Heterogeneous Systems with the Tribble Source-to-Source Framework.

Luís Miguel Sousa, João Bispo, Nuno Paulino

Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022

A Dataset of Phase Samples using an 8-Element Uniform Circular Antenna Array and a Bluetooth Low Energy 5.1 Nordic nRF52811 Based Receiver.

Nuno Paulino

Dataset, November, 2022

A Batch of Integer Data Sets for Clustering Algorithms.

Nuno Paulino

Dataset, May, 2022

Design and Experimental Evaluation of a Bluetooth 5.1 Antenna Array for Angle-of-Arrival Estimation.

Nuno Paulino, Luís M. Pessoa, André Branquinho, Edgar Gonçalves

Proceedings of the 13th International Symposium on Communication Systems, 2022

2021

A Binary Translation Framework for Automated Hardware Generation.

Nuno Paulino, João Bispo, João Canas Ferreira, João M. P. Cardoso

IEEE Micro, 2021

Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey.

Nuno Paulino, João Canas Ferreira, João M. P. Cardoso

ACM Comput. Surv., 2021

A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA.

Luís Miguel Sousa, Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo

CoRR, 2021

Optimizing Packet Reception Rates for Low Duty-Cycle BLE Relay Nodes.

Nuno Miguel Cardanha Paulino, Luís M. Pessoa, André Branquinho, Rafael Tavares, Igor Ferreira

CoRR, 2021

Multiple target tracking with interaction using an MCMC MRF Particle Filter.

Hélder F. S. Campos, Nuno Paulino

CoRR, 2021

Augmentation of base classifier performance via HMMs on a handwritten character data set.

Hélder Campos, Nuno Paulino

CoRR, 2021

Building Beyond HLS: Graph Analysis and Others.

Pedro Filipe Silva, João Bispo, Nuno Miguel Cardanha Paulino

CoRR, 2021

FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example.

Pedro Filipe Silva, João Bispo, Nuno Paulino

Proceedings of the International Conference on Field-Programmable Technology, 2021

On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators.

Tiago Santos, Nuno Paulino, João Bispo, João M. P. Cardoso, João Canas Ferreira

Proceedings of the International Conference on Field-Programmable Technology, 2021

Evaluating a Novel Bluetooth 5.1 AoA Approach for Low-Cost Indoor Vehicle Tracking via Simulation.

Nuno Paulino, Luís M. Pessoa, André Branquinho, Edgar Gonçalves

Proceedings of the Joint European Conference on Networks and Communications & 6G Summit, 2021

2020

Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets.

Nuno Paulino, João Canas Ferreira, João M. P. Cardoso

IEEE Access, 2020

Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework.

Nuno Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

Dynamic Partial Reconfiguration of Customized Single-Row Accelerators.

Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso

IEEE Trans. Very Large Scale Integr. Syst., 2019

2017

Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces.

Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso

IEEE Trans. Very Large Scale Integr. Syst., 2017

On Coding Techniques for Targeting FPGAs via OpenCL.

Nuno Paulino, Luís Reis, João M. P. Cardoso

Proceedings of the Parallel Computing is Everywhere, 2017

2016

Generation of Custom Run-Time Reconfigurable Hardware for Transparent Binary Acceleration

Nuno Miguel Cardanha Paulino

PhD thesis, 2016

2015

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses.

Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso

ACM Trans. Reconfigurable Technol. Syst., 2015

Transparent acceleration of program execution using reconfigurable hardware.

Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support.

Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Manuel Paiva Cardoso

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

2013

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems.

João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira

IEEE Trans. Ind. Informatics, 2013

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units.

João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira

Int. J. Reconfigurable Comput., 2013

Architecture for Transparent Binary Acceleration of Loops with Memory Accesses.

Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2011

From Instruction Traces to Specialized Reconfigurable Arrays.

João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011