Nuno Miguel Cardanha Paulino

Orcid: 0000-0001-5547-0323

Affiliations:
  • University of Porto, Department of Informatics Engineering, Portugal


According to our database1, Nuno Miguel Cardanha Paulino authored at least 36 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2024
Vision-Radio Experimental Infrastructure Architecture Towards 6G.
CoRR, 2024

Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study.
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024

SpecRF-Posture: Exploring Specular Reflections for Human Posture Recognition.
Proceedings of the IEEE International Mediterranean Conference on Communications and Networking, 2024

CONVERGE: A Vision-Radio Research Infrastructure Towards 6G and Beyond.
Proceedings of the Joint European Conference on Networks and Communications & 6G Summit, 2024

A Deep Learning Approach in RIS-based Indoor Localization.
Proceedings of the Joint European Conference on Networks and Communications & 6G Summit, 2024

A DSL and MLIR Dialect for Streaming and Vectorisation.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023
Self-Localization via Circular Bluetooth 5.1 Antenna Array Receiver.
IEEE Access, 2023

Challenges and Opportunities in C/C++ Source-To-Source Compilation (Invited Paper).
Proceedings of the 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2023

Enhancing NLoS RIS-Aided Localization with Optimization and Machine Learning.
Proceedings of the IEEE Globecom Workshops 2023, 2023

Retargeting Applications for Heterogeneous Systems with the Tribble Source-to-Source Framework.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022
A Dataset of Phase Samples using an 8-Element Uniform Circular Antenna Array and a Bluetooth Low Energy 5.1 Nordic nRF52811 Based Receiver.
Dataset, November, 2022

A Batch of Integer Data Sets for Clustering Algorithms.
Dataset, May, 2022

Design and Experimental Evaluation of a Bluetooth 5.1 Antenna Array for Angle-of-Arrival Estimation.
Proceedings of the 13th International Symposium on Communication Systems, 2022

2021
A Binary Translation Framework for Automated Hardware Generation.
IEEE Micro, 2021

Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey.
ACM Comput. Surv., 2021

A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA.
CoRR, 2021

Optimizing Packet Reception Rates for Low Duty-Cycle BLE Relay Nodes.
CoRR, 2021

Multiple target tracking with interaction using an MCMC MRF Particle Filter.
CoRR, 2021

Augmentation of base classifier performance via HMMs on a handwritten character data set.
CoRR, 2021

Building Beyond HLS: Graph Analysis and Others.
CoRR, 2021

FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example.
Proceedings of the International Conference on Field-Programmable Technology, 2021

On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators.
Proceedings of the International Conference on Field-Programmable Technology, 2021

Evaluating a Novel Bluetooth 5.1 AoA Approach for Low-Cost Indoor Vehicle Tracking via Simulation.
Proceedings of the Joint European Conference on Networks and Communications & 6G Summit, 2021

2020
Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets.
IEEE Access, 2020

Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019
Dynamic Partial Reconfiguration of Customized Single-Row Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2017
Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces.
IEEE Trans. Very Large Scale Integr. Syst., 2017

On Coding Techniques for Targeting FPGAs via OpenCL.
Proceedings of the Parallel Computing is Everywhere, 2017

2016
Generation of Custom Run-Time Reconfigurable Hardware for Transparent Binary Acceleration
PhD thesis, 2016

2015
A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses.
ACM Trans. Reconfigurable Technol. Syst., 2015

Transparent acceleration of program execution using reconfigurable hardware.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

2013
Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems.
IEEE Trans. Ind. Informatics, 2013

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units.
Int. J. Reconfigurable Comput., 2013

Architecture for Transparent Binary Acceleration of Loops with Memory Accesses.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2011
From Instruction Traces to Specialized Reconfigurable Arrays.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011


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