Nuno Lourenço

According to our database, Nuno Lourenço authored at least 82 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Design Automation of Analog and Mixed-Signal Circuits Using Neural Networks - A Tutorial Brief.

Gustavo Liñán Cembrano, Nuno Lourenço, Nuno Horta, José M. de la Rosa

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

A 25 nW Heartbeat Monitoring Circuit for Wearable Applications in CMOS 65nm.

Rafael Vieira, Seyedehsomayeh Hatefinasab, Ricardo Martins, Nuno Horta, Nuno Lourenço

Proceedings of the 20th International Conference on Synthesis, 2024

Effective Routing Probability Maps via Convolutional Neural Networks for Analog IC Layout Automation.

Diogo Peneda, Filipe Azevedo, Nuno Lourenço, Nuno Horta, Ricardo Martins

Proceedings of the 20th International Conference on Synthesis, 2024

Low-Power 9.6-11GHz and 10.8-12GHz VCOs Designed for a 2.5/5GHz TRx using High-Q Inductors Synthesized with ML Techniques.

Fábio Passos, Ricardo M. F. Martins, Nuno Lourenço

Proceedings of the 20th International Conference on Synthesis, 2024

Ponderous: A Performance-driven Analog IC Placement Optimizer Leveraged by a ML Pipeline.

Ricardo Martins, António Gusmão, Rafael Vieira, Fábio Passos, Nuno Lourenço, Nuno Horta

Proceedings of the 20th International Conference on Synthesis, 2024

2023

Behavioral Analysis of Noise and Bandwidth Specifications of Heartbeat Detection Circuits for Ultra Low Power Devices.

Rafael Vieira, Fábio Passos, Ricardo Martins, Nuno Horta, Nuno Lourenço

IEEE Access, 2023

Analog Integrated Circuit Routing Techniques: An Extensive Review.

Ricardo M. F. Martins, Nuno Lourenço

IEEE Access, 2023

Design Space Exploration of Single-Stage OTAs towards an Ultra-Low-Power LNA for ECG Signals.

Rafael Vieira, Ricardo Martins, Nuno Horta, Nuno Lourenço

Proceedings of the 19th International Conference on Synthesis, 2023

A 23.5-32.5GHz, 17dBm PSAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology.

Fábio Passos, Nuno Lourenço, Luís Mendes, Ricardo Martins, João Caldinhas Vaz, Nuno Horta

Proceedings of the 19th International Conference on Synthesis, 2023

An ANN-Based Approach to the Modelling and Simulation of Analogue Circuits.

André Amaral, António Gusmão, Rafael Vieira, Ricardo Martins, Nuno Horta, Nuno Lourenço

Proceedings of the 19th International Conference on Synthesis, 2023

Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models.

Fábio Passos, Nuno Lourenço, Luís Mendes, Ricardo Martins, João Caldinhas Vaz, Nuno Horta

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Scalable and order invariant analog integrated circuit placement with Attention-based Graph-to-Sequence deep models.

António Paiva Lapas de Gusmão, Nuno Cavaco Gomes Horta, Nuno Calado Correia Lourenço, Ricardo Miguel Ferreira Martins

Expert Syst. Appl., 2022

DeepPlacer: A custom integrated OpAmp placement tool using deep models.

António Gusmão, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins

Appl. Soft Comput., 2022

Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling.

Rafael Vieira, Fábio Passos, Ricardo Povoa, Ricardo Martins, Nuno Horta, Jorge Guilherme, Nuno Lourenço

Proceedings of the 18th International Conference on Synthesis, 2022

Machine Learning Approaches for Transformer Modeling.

Fábio Passos, Nuno C. Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández

Proceedings of the 18th International Conference on Synthesis, 2022

Accelerating Voltage-Controlled Oscillator Sizing Optimizations with ANN-based Convergence Classifiers and Frequency Guess Predictors.

João Domingues, António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins

Proceedings of the 18th International Conference on Synthesis, 2022

ANN-based Analog IC Floorplan Recommender with a Broader Topological Constraints Coverage.

Pedro Alves, António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins

Proceedings of the 18th International Conference on Synthesis, 2022

Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/°C Temperature Coefficient.

Nuno Lourenço, Fábio Passos, Rafael Vieira, Ricardo Martins, Nuno Horta, Jorge Guilherme, Ricardo Póvoa

Proceedings of the 18th International Conference on Synthesis, 2022

Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator based on ANNs.

Pedro Vaz, António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/°C Stability for Space Applications.

Fábio Passos, Rafael Vieira, António Canelas, Ricardo Póvoa, Nuno Lourenço, Nuno Horta, Jorge Guilherme

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS.

Luís Mendes, João Caldinhas Vaz, Fábio Passos, Nuno Lourenço, Ricardo Martins

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test.

Engin Afacan, Nuno Lourenço, Ricardo Martins, Günhan Dündar

Integr., 2021

Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing.

Ricardo Martins, Nuno Lourenço, Ricardo Póvoa, Nuno Horta

Eng. Appl. Artif. Intell., 2021

In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization.

Luís Mendes, João Caldinhas Vaz, Fábio Passos, Nuno Lourenço, Ricardo Martins

IEEE Access, 2021

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs.

António Canelas, Fábio Passos, Nuno Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández

IEEE Access, 2021

Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement.

António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications.

Ricardo Póvoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools.

Ricardo Martins, Nuno Lourenço, Nuno Horta, Shenke Zhong, Jun Yin, Pui-In Mak, Rui Paulo Martins

IEEE Trans. Circuits Syst., 2020

FUZYE: A Fuzzy <i>c</i>-Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms.

António Canelas, Ricardo Póvoa, Ricardo Martins, Nuno Lourenço, Jorge Guilherme, João Paulo Carvalho, Nuno Horta

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications.

Ricardo Póvoa, Richa Arya, António Canelas, Fábio Passos, Ricardo Martins, Nuno Lourenço, Nuno Horta

Microelectron. J., 2020

A new family of CMOS inverter-based OTAs for biomedical and healthcare applications.

Ricardo Póvoa, António Canelas, Ricardo Martins, Nuno Horta, Nuno Lourenço, João Goes

Integr., 2020

Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology.

Fábio Passos, Elisenda Roca, Ricardo Martins, Nuno Lourenço, Saiyd Ahyoune, Javier J. Sieiro, Rafael Castro-López, Nuno Horta, Francisco V. Fernández

IEEE Access, 2020

Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender.

António Gusmão, Fábio Passos, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Analog IC Placement Generation via Neural Networks from Unlabeled Data

António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins

Springer, ISBN: 978-3-030-50060-3, 2020

2019

Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications.

Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins

IEEE Trans. Very Large Scale Integr. Syst., 2019

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop.

Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers.

Ricardo Póvoa, António Canelas, Ricardo Martins, Nuno Horta, Nuno Lourenço, João Goes

Proceedings of the 16th International Conference on Synthesis, 2019

Artificial Neural Networks as an Alternative for Automatic Analog IC Placement.

Daniel Guerra, António Canelas, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins

Proceedings of the 16th International Conference on Synthesis, 2019

Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing.

Nuno Lourenço, Engin Afacan, Ricardo Martins, Fábio Passos, António Canelas, Ricardo Póvoa, Nuno Horta, Günhan Dündar

Proceedings of the 16th International Conference on Synthesis, 2019

On the Exploration of Design Tradeoffs in Analog IC Placement with Layout-dependent Effects.

Ricardo Martins, Nuno Lourenço, Ricardo Póvoa, Nuno Horta

Proceedings of the 16th International Conference on Synthesis, 2019

Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm.

Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins

Proceedings of the 16th International Conference on Synthesis, 2019

Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization.

Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Póvoa, Nuno Horta, Emmanuel Moutaye

Proceedings of the 16th International Conference on Synthesis, 2019

2018

Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving.

Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement.

Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Cavaco Gomes Horta, João Goes

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology.

Fábio Passos, Ricardo Martins, Nuno Lourenço, Elisenda Roca, Ricardo Povoa, António Canelas, Rafael Castro-López, Nuno Horta, Francisco V. Fernández

Integr., 2018

Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs.

Fábio Passos, Ricardo Martins, Nuno C. Lourenço, Elisenda Roca, Rafael Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández

Proceedings of the 15th International Conference on Synthesis, 2018

A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications.

António Canelas, Ricardo Povoa, Ricardo M. F. Martins, Nuno Lourenço, Jorge Guilherme, Nuno Horta

Proceedings of the 15th International Conference on Synthesis, 2018

On the Exploration of Promising Analog IC Designs via Artificial Neural Networks.

Nuno Lourenço, Joao Rosa, Ricardo Martins, Helena Aidos, António Canelas, Ricardo Povoa, Nuno Horta

Proceedings of the 15th International Conference on Synthesis, 2018

Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications.

Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins

Proceedings of the 15th International Conference on Synthesis, 2018

Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel.

Tiago Pessoa, Nuno Lourenço, Ricardo Martins, Ricardo Povoa, Nuno Horta

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Stochastic-based placement template generator for analog IC layout-aware synthesis.

Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta

Integr., 2017

Systematic design of a voltage controlled oscillator using a layout-aware approach.

Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno C. G. Horta

Proceedings of the 14th International Conference on Synthesis, 2017

Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks.

Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández

Proceedings of the 14th International Conference on Synthesis, 2017

New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization.

Nuno C. Lourenço, Ricardo Martins, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández

Proceedings of the 14th International Conference on Synthesis, 2017

Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing.

António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Automatic technology migration of analog IC designs using generic cell libraries.

Jose Cachaco, Nuno Machado, Nuno Lourenço, Jorge Guilherme, Nuno Horta

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques.

Ricardo Povoa, Ivan Bastos, Nuno Lourenço, Nuno Horta

Integr., 2016

Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer.

Mrinalinee Pandey, António Canelas, Ricardo Póvoa, Jorge Alves Torres, João Costa Freire, Nuno Lourenço, Nuno Horta

Integr., 2016

Current-flow and current-density-aware multi-objective optimization of analog IC placement.

Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta

Integr., 2016

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation.

Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Povoa, Nuno Horta

Integr., 2016

Automated analog IC design constraints generation for a layout-aware sizing approach.

Andre Ferreira, Nuno Lourenço, Ricardo Martins, Nuno Horta

Proceedings of the 13th International Conference on Synthesis, 2016

Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations.

António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta

Proceedings of the 13th International Conference on Synthesis, 2016

On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies.

Ricardo Martins, António Canelas, Nuno Lourenço, Nuno Horta

Proceedings of the 13th International Conference on Synthesis, 2016

Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach.

David Neves, Ricardo Martins, Nuno Lourenço, Nuno Horta

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Floorplan-aware analog IC sizing and optimization based on topological constraints.

Nuno Lourenço, António Canelas, Ricardo Povoa, Ricardo Martins, Nuno Horta

Integr., 2015

Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates.

Ricardo Martins, Nuno Lourenço, Nuno Horta

Expert Syst. Appl., 2015

A voltage-combiners-biased amplifier with enhanced gain and speed using current starving.

Ricardo Povoa, Nuno Lourenço, Nuno Horta, João Goes

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Extraction and application of wiring symmetry rules to route analog multiport terminals.

Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction.

Nuno Lourenço, Ricardo Martins, Nuno Horta

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Electromigration-aware analog Router with multilayer multiport terminal structures.

Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta

Integr., 2014

LC-VCO automatic synthesis using multi-objective evolutionary techniques.

Ricardo Povoa, Ricardo Lourenco, Nuno Lourenço, António Canelas, Ricardo Martins, Nuno Horta

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A cascode-free single-stage amplifier using a fully-differential folded voltage-combiner.

Ricardo Povoa, Nuno Lourenço, Nuno Horta, Rui Santos-Tavares, João Goes

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures.

Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

LAYGEN II - Automatic Layout Generation of Analog Integrated Circuits.

Ricardo Martins, Nuno Lourenço, Nuno Horta

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners.

Ricardo Povoa, Nuno Lourenço, Nuno Horta, Rui Santos-Tavares, João Goes

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel.

Frederico Rocha, Ricardo Martins, Nuno Lourenço, Nuno Horta

Proceedings of the Technological Innovation for the Internet of Things, 2013

A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis.

Frederico Rocha, Nuno Lourenço, Ricardo Povoa, Ricardo Martins, Nuno Horta

Proceedings of the IEEE Congress on Evolutionary Computation, 2013

Multi-port multi-terminal analog router based on an evolutionary optimization kernel.

Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta

Proceedings of the IEEE Congress on Evolutionary Computation, 2013

2012

LAYGEN II: automatic analog ICs layout generator based on a template approach.

Ricardo Martins, Nuno Lourenço, Nuno Horta

Proceedings of the Genetic and Evolutionary Computation Conference, 2012

GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation.

Nuno Lourenço, Nuno Horta

Proceedings of the Genetic and Evolutionary Computation Conference, 2012

2007

Automatic analog IC layout generation based on a evolutionary computation approach.

Nuno C. Lourenço, Nuno C. G. Horta

Proceedings of the Genetic and Evolutionary Computation Conference, 2007

2005

Laygen - An evolutionary approach to automatic analog IC layout generation.

Nuno Lourenço, Nuno Horta

Proceedings of the 12th IEEE International Conference on Electronics, 2005