Nozar Tabrizi

According to our database1, Nozar Tabrizi authored at least 13 papers between 1996 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
Fostering an entrepreneurial mindset in "digital systems" class through a jigsaw-puzzle model.
Proceedings of the 2017 IEEE Frontiers in Education Conference, 2017

Fostering an entrepreneurial mindset in "computer architecture and organization" class through a producer-customer model.
Proceedings of the 2017 IEEE Global Engineering Education Conference, 2017

2016
Fostering an Entrepreneurial mindset in "Digital Systems" class through a Producer-Customer model.
Proceedings of the 2016 IEEE Frontiers in Education Conference, 2016

2008
An ASIC design and formal analysis of a novel pipelined and parallel sorting accelerator.
Integr., 2008

2005
A Programmable DSP Architecture for Wireless Communication Systems.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
MaRS: a macro-pipelined reconfigurable system.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
Algorithm optimizations and mapping scheme for interactive ray tracing on a reconfigurable architecture.
Comput. Graph., 2003

Interactive ray tracing on reconfigurable SIMD MorphoSys.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Interactive Ray Tracing on Reconfigurable SIMD Morphosys.
Proceedings of the Embedded Software for SoC, 2003

2002
Interactive Ray Tracing Using a SIMD Reconfigurable Architecture.
Proceedings of the 14th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2002), 2002

1997
A Tabular Method for Guard Strengthening, Symmetrization, and Operator Reduction for Martin's Asynchronous Design Methodology.
IEEE Trans. Computers, 1997

1996
Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Dynamic hazards and speed independent delay model.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996


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