Nouri Masmoudi

IET Image Process., 2016

Statistical analysis of SHVC encoded video.

[BibT_eX]

[DOI]

Proceedings of the International Image Processing, Applications and Systems, 2016

FPGA implementation of improved binarizer design for context-based adaptive binary arithmetic coder.

[BibT_eX]

[DOI]

Proceedings of the International Image Processing, Applications and Systems, 2016

SAD and SSE implementation for HEVC encoder on DSP TMS320C6678.

[BibT_eX]

[DOI]

Proceedings of the International Image Processing, Applications and Systems, 2016

Fast motion estimation for HEVC video coding.

[BibT_eX]

[DOI]

Proceedings of the International Image Processing, Applications and Systems, 2016

An optimized and unified architecture design for H.265/HEVC 1-D inverse core transform.

[BibT_eX]

[DOI]

Proceedings of the International Image Processing, Applications and Systems, 2016

A comparative study of GOM, uLBP, VLC and fractional Eigenfaces for face recognition.

[BibT_eX]

[DOI]

Proceedings of the International Image Processing, Applications and Systems, 2016

Statistical analysis on coding unit partition of HEVC encoded HD videos.

[BibT_eX]

[DOI]

Proceedings of the International Image Processing, Applications and Systems, 2016

Reduction in CABAC encoding time of the HEVC.

[BibT_eX]

[DOI]

Proceedings of the International Image Processing, Applications and Systems, 2016

Statistical analysis of intra prediction in HEVC video encoder.

[BibT_eX]

[DOI]

Proceedings of the International Image Processing, Applications and Systems, 2016

A pretreatment using saliency map Harris to improve MSU blocking metric performance for encoding H264 / AVC : Saliency map for video quality assessment.

[BibT_eX]

[DOI]

Mohamed Ben Amor

Fahmi Kammoun

Nouri Masmodi

Proceedings of the International Image Processing, Applications and Systems, 2016

An optimized hardware architecture of 4×4, 8×8, 16×16 and 32×32 inverse transform for HEVC.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Conference on Advanced Technologies for Signal and Image Processing, 2016

New PLL architecture based on sample and hold phase detector without neither filter nor Inverse Sine circuit.

[BibT_eX]

[DOI]

Bilel Gassara

Proceedings of the 13th International Multi-Conference on Systems, Signals & Devices, 2016

2015

A Robust Iris Feature Extraction Approach Based on Monogenic and 2D Log-Gabor Filters.

[BibT_eX]

[DOI]

J. Intell. Syst., 2015

FPGA-Based Design Δ-Σ Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit.

[BibT_eX]

[DOI]

Noura Ben Ameur

Mourad Loulou

J. Circuits Syst. Comput., 2015

H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2015

An efficient hardware architecture for interpolation filter of HEVC decoder.

[BibT_eX]

[DOI]

Manel Kammoun

Proceedings of the 12th IEEE International Multi-Conference on Systems, Signals & Devices, 2015

HLS based design of a mixed architecture for H.264/AVC CAVLD.

[BibT_eX]

[DOI]

Taheni Damak

Sébastien Bilavarn

Proceedings of the 12th IEEE International Multi-Conference on Systems, Signals & Devices, 2015

SW implementation of video coding using open virtual platform.

[BibT_eX]

[DOI]

Mokhtar Bouain

Proceedings of the 12th IEEE International Multi-Conference on Systems, Signals & Devices, 2015

2014

MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder.

[BibT_eX]

[DOI]

Int. J. Embed. Real Time Commun. Syst., 2014

A fast CU Partitionning algorithm based on early detection of zero block quantified transform coefficients for HEVC standard.

[BibT_eX]

[DOI]

Proceedings of the International Image Processing, 2014

A very efficient encryption scheme for the H.264/AVC CODEC adopted in Intra prediction mode.

[BibT_eX]

[DOI]

Proceedings of the International Image Processing, 2014

An optimized hardware architecture for intra prediction for HEVC.

[BibT_eX]

[DOI]

Manel Kammoun

Proceedings of the International Image Processing, 2014

A block artifact distortion measure for no reference video quality evaluation.

[BibT_eX]

[DOI]

Mohamed Ben Amor

Mohamed-Chaker Larabi

Fahmi Kammoun

Proceedings of the International Image Processing, 2014

TZSearch pattern search improvement for HEVC motion estimation modules.

[BibT_eX]

[DOI]

Proceedings of the 2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2014

Motion vectors signs encryption for H.264/AVC.

[BibT_eX]

[DOI]

Proceedings of the 2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2014

DSP-based down-sampling process using lanczos filter bank.

[BibT_eX]

[DOI]

Proceedings of the 2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2014

Automatic Hardware/Software interface generation for SynDEx-mixte.

[BibT_eX]

[DOI]

Proceedings of the 2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2014

MPSoC architecture for Component Level Parallelism of H.264/AVC intra prediction encoding chain on SoCLib platform.

[BibT_eX]

[DOI]

Proceedings of the 2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2014

2013

Reconfigurable architecture of VDF filter for multidimensional data.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2013

A CABAC codec of H.264AVC with secure arithmetic coding.

[BibT_eX]

[DOI]

Proceedings of the Real-Time Image and Video Processing 2013, 2013

Design and FPGA-based multi-channel, low phase-jitter ADPLL for audio data converter.

[BibT_eX]

[DOI]

Noura Ben Ameur

Mourad Loulou

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Evaluation and implementation of simultaneous binary arithmetic coding and encryption for HD H264/AVC codec.

[BibT_eX]

[DOI]

Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

An efficient architecture VLSI for 4×4 intra prediction in HEVC standard.

[BibT_eX]

[DOI]

Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

Free multiplication integer transformation for the HEVC standard.

[BibT_eX]

[DOI]

Fatma Belghith

Hassen Loukil

Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

2012

Implementation and Optimization of an Enhanced PWD Metric for H.264/AVC on a TMS320C64 DSP.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

FPGA architecture of the LDPS Motion Estimation for H.264/AVC Video Coding.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

Real-time H.264/AVC baseline decoder implementation on TMS320C6416.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2012

A Fast and Accurate Eyelids and Eyelashes Detection Approach for Iris Segmentation.

[BibT_eX]

[DOI]

Walid Aydi

Lotfi Kamoun

J. Multim. Process. Technol., 2012

Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

2011

An Efficient Spatial Scalable Video Encoder Based on DWT.

[BibT_eX]

[DOI]

Saoussen Cheikhrouhou

Yousra Ben Jemaa

Proceedings of the Signal Processing and Information Technology, 2011

High level characterization and optimization of a GPSK modulator with genetic algorithm.

[BibT_eX]

[DOI]

Salwa Fakhfakh Sahnoun

Ahmed Fakhfakh

Hervé Levi

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

HW/SW TQ/IQT design for H.264/AVC.

[BibT_eX]

[DOI]

Hassen Loukil

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010

Optimal DSP Based Integer Motion Estimation Implementation for H.264/AVC Baseline Encoder.

[BibT_eX]

[DOI]

Int. Arab J. Inf. Technol., 2010

Implementation of Vector Directional Distance Rational Hybrid Filter Using TMS320C6416.

[BibT_eX]

[DOI]

Anis Boudabous

Lazhar Khriji

Int. Arab J. Inf. Technol., 2010

HW/SW Design-Based Implementation of Vector Median Rational Hybrid Filter.

[BibT_eX]

[DOI]

Int. Arab J. Inf. Technol., 2010

FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder.

[BibT_eX]

[DOI]

Circuits Syst., 2010

2009

Toward an optimal residual frame coding for DWT based video codec.

[BibT_eX]

[DOI]

Saoussen Cheikhrouhou

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

FPGA implementation of a HW/SW platform for multimedia embedded systems.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2008

DSP CAVLC implementation and optimization for H.264/AVC baseline encoder.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

Toward an Optimal Block Motion Estimation Algorithm for H.264/AVC.

[BibT_eX]

[DOI]

Amine Samet

Int. J. Image Graph., 2007

Signal Processing H.264/AVC prediction modules complexity analysis.

[BibT_eX]

[DOI]

Amine Samet

Eur. Trans. Telecommun., 2007

HW/SW FPGA Architecture for a Flexible Motion Estimation.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

Analysis and Optimization of UB Video's H.264 Baseline Encoder Implementation on Texas Instruments' TMS320DM642 DSP.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2006

An Efficient HW/SW Implementation of the H.263 Video Coder in FPGA.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Optimization and Implementation on Fpga of the DCT/IDCT Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

HW/SW Codesign of the H.263 Video Coder.

[BibT_eX]

[DOI]

Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005

High order cascade multibit σΔ modulator for wide bandwidth applications.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Electronics, 2005

Optimization of a fractional-N frequency synthesizer with a VHDL-AMS description using the "experience plan" method.

[BibT_eX]

[DOI]

Sonia Eloued

Ahmed Fakhfakh

Proceedings of the 12th IEEE International Conference on Electronics, 2005

Top-down hierarchical design flow application.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2005

VHDL-AMS virtual prototyping in power electronics.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2005

2004

Perceptual Evaluation of JPEG2000.

[BibT_eX]

[DOI]

Eur. Trans. Telecommun., 2004

High Level Self-adjusted Models and VHDL-AMS; Application for a freguency synthesizer modelling.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2004

2003

Settling accuracy and noise performances in switched current grounded gate class AB memory cells.

[BibT_eX]

[DOI]

Mourad Fakhfakh

Mourad Loulou

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

VHDL-AMS Behavioural Modelling of a Switched Current Sigma-Delta Modulator.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2003

2002

Electronic control in electric vehicle based on CAN network.

[BibT_eX]

[DOI]

Lamia Chaari

Lotfi Kamoun

Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, Yasmine Hammamet, Tunisia, October 6-9, 2002, 2002

2001

On the validity of the standard SPICE model of the diode for simulation in power electronics.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2001

A new method to implement CORDIC algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

New parallel architecture of the DCT and its inverse for image compression.

[BibT_eX]

[DOI]

M. Bousselmi

Mohamed Salim Bouhlel