Noureddine Chabini
According to our database1,
Noureddine Chabini
authored at least 43 papers
between 2001 and 2024.
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Bibliography
2024
Proceedings of the 15th IEEE Annual Ubiquitous Computing, 2024
2023
An Efficient FPGA-Based Gaussian Random Number Generator Using an Accurate Segmented Box-Muller Method.
IEEE Access, 2023
Proceedings of the 13th IEEE Annual Computing and Communication Workshop and Conference, 2023
Comparing FPGA-Based Adders and Application to the Implementation of a Digital FIR Filter.
Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2023
Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2023
Path Balancing for Reducing Dynamic Power Consumption in Digital Designs Containing IP-Blocks.
Proceedings of the 2023 IEEE World AI IoT Congress (AIIoT), 2023
2022
Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures.
Comput. Electr. Eng., 2022
An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs.
Proceedings of the 3rd IEEE International Conference on Electronics, 2022
Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2022
2021
Efficient FPGA based architecture for high-order FIR filtering using simultaneous DSP and LUT reduced utilization.
IET Circuits Devices Syst., 2021
2020
Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture.
J. Circuits Syst. Comput., 2020
2017
VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing.
J. Circuits Syst. Comput., 2017
Int. J. Reconfigurable Comput., 2017
Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
2015
Proceedings of the 27th International Conference on Microelectronics, 2015
Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders.
Proceedings of the 12th IEEE/ACS International Conference of Computer Systems and Applications, 2015
2013
Design optimization of the quantization and a pipelined 2D-DCT for real-time applications.
Multim. Tools Appl., 2013
2012
IET Comput. Digit. Tech., 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
2011
Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction bus.
IET Comput. Digit. Tech., 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
2010
J. Signal Process. Syst., 2010
2009
Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs.
Int. J. Reconfigurable Comput., 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2007
Optimised realisations of large integer multipliers and squarers using embedded blocks.
IET Comput. Digit. Tech., 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007
Proceedings of the 25th International Conference on Computer Design, 2007
An approach for computing the initial state for retimed synchronous sequential circuits.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers.
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006
2005
Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques.
ACM Trans. Design Autom. Electr. Syst., 2005
2004
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2004
Proceedings of the EMSOFT 2004, 2004
An approach for reducing dynamic power consumption in synchronous sequential digital designs.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Proceedings of the Embedded Software, Third International Conference, 2003
2001
Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001