Noureddine Chabini

According to our database, Noureddine Chabini authored at least 42 papers between 2001 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

An Efficient FPGA-Based Gaussian Random Number Generator Using an Accurate Segmented Box-Muller Method.

Samir Dahmani, Mountassar Maamoun, Ghania Zerari, Noureddine Chabini, Rachid Beguenane

IEEE Access, 2023

FPGA-Based Digital FIR Filters With Small Coefficients and Large Data Input.

Noureddine Chabini, Rachid Beguenane

Proceedings of the 13th IEEE Annual Computing and Communication Workshop and Conference, 2023

Comparing FPGA-Based Adders and Application to the Implementation of a Digital FIR Filter.

Justin Woelfle, Noureddine Chabini, Rachid Beguenane

Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2023

FPGA-Based 8x8 Bits Signed Multipliers Using LUTs.

Noureddine Chabini, Rachid Beguenane

Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2023

Path Balancing for Reducing Dynamic Power Consumption in Digital Designs Containing IP-Blocks.

Noureddine Chabini, Marilyn Claire Wolf

Proceedings of the 2023 IEEE World AI IoT Congress (AIIoT), 2023

2022

Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures.

Mohamed Najoui, Mounir Bahtat, Abdessamad Klilou, Anas Hatim, Said Belkouch, Atman Jbari, Noureddine Chabini

Comput. Electr. Eng., 2022

An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs.

Noureddine Chabini, Said Belkouch, Mohamed Najoui

Proceedings of the 3rd IEEE International Conference on Electronics, 2022

FPGA-Based Designs of the Factorial Function.

Noureddine Chabini, Rachid Beguenane

Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2022

2021

Efficient FPGA based architecture for high-order FIR filtering using simultaneous DSP and LUT reduced utilization.

Mountassar Maamoun, Adnane Hassani, Samir Dahmani, Hocine Ait Saadi, Ghania Zerari, Noureddine Chabini, Rachid Beguenane

IET Circuits Devices Syst., 2021

2020

Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture.

Mohamed Najoui, Anas Hatim, Said Belkouch, Noureddine Chabini

J. Circuits Syst. Comput., 2020

2017

VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing.

Mohamed Najoui, Mounir Bahtat, Anas Hatim, Said Belkouch, Noureddine Chabini

J. Circuits Syst. Comput., 2017

Efficient Realization of BCD Multipliers Using FPGAs.

Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini

Int. J. Reconfigurable Comput., 2017

Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier.

Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini

Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2015

Reducing the number of embedded multipliers in squaring large size complex numbers.

Fatima-Ezzahra Guessous, Noureddine Chabini

Proceedings of the 27th International Conference on Microelectronics, 2015

Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders.

Noureddine Chabini, Said Belkouch

Proceedings of the 12th IEEE/ACS International Conference of Computer Systems and Applications, 2015

2013

Design optimization of the quantization and a pipelined 2D-DCT for real-time applications.

Anas Hatim, Said Belkouch, Mohamed El Aakif, Moha M'rabet Hassani, Noureddine Chabini

Multim. Tools Appl., 2013

2012

Asymmetric large size multipliers with optimised FPGA resource utilisation.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois

IET Comput. Digit. Tech., 2012

An improved BCD adder using 6-LUT FPGAs.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011

Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction bus.

Noureddine Chabini, Marilyn Wolf

IET Comput. Digit. Tech., 2011

Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010

FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers.

Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois

J. Signal Process. Syst., 2010

2009

Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini

Int. J. Reconfigurable Comput., 2009

Two level decomposition based matrix multiplication for FPGAs.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2007

Optimised realisations of large integer multipliers and squarers using embedded blocks.

Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois

IET Comput. Digit. Tech., 2007

A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs.

Noureddine Chabini

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints.

Noureddine Chabini, Wayne H. Wolf

Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Register binding guided by the size of variables.

Noureddine Chabini, Wayne H. Wolf

Proceedings of the 25th International Conference on Computer Design, 2007

An approach for computing the initial state for retimed synchronous sequential circuits.

Noureddine Chabini, Wayne H. Wolf

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers.

Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers.

Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois

Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

2005

Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints.

Noureddine Chabini, Wayne H. Wolf

IEEE Trans. Very Large Scale Integr. Syst., 2005

Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques.

Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria

ACM Trans. Design Autom. Electr. Syst., 2005

2004

Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling.

Noureddine Chabini, Wayne H. Wolf

IEEE Trans. Very Large Scale Integr. Syst., 2004

An approach for integrating basic retiming and software pipelining.

Noureddine Chabini, Wayne H. Wolf

Proceedings of the EMSOFT 2004, 2004

An approach for reducing dynamic power consumption in synchronous sequential digital designs.

Noureddine Chabini, Wayne H. Wolf

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages.

Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs.

Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Minimizing Variables' Lifetime in Loop-Intensive Applications.

Noureddine Chabini, Wayne H. Wolf

Proceedings of the Embedded Software, Third International Conference, 2003

2001

Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques.

Noureddine Chabini, Yvon Savaria

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages.

Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001