Noritsugu Nakamura

According to our database, Noritsugu Nakamura authored at least 7 papers between 2000 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications.

Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2016

Constructing a Human-like agent for the Werewolf Game using a psychological model based multiple perspectives.

Noritsugu Nakamura, Michimasa Inaba, Kenichi Takahashi, Fujio Toriumi, Hirotaka Osawa, Daisuke Katagami, Kousuke Shinoda

Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016

2013

Optimizing time and space multiplexed computation in a dynamically reconfigurable processor.

Takao Toi, Noritsugu Nakamura, Taro Fujii, Toshiro Kitaoka, Katsumi Togawa, Koichiro Furuta, Toru Awashima

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2010

High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor.

Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi

IPSJ Trans. Syst. LSI Des. Methodol., 2010

2006

High-level synthesis challenges and solutions for a dynamically reconfigurable processor.

Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2001

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield.

Kenji Noda, Koichi Takeda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi

IEEE J. Solid State Circuits, 2001

2000

A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro.

Koichi Takeda, Yoshiharu Aimoto, Noritsugu Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Kenji Noda, Koujirou Matsui, Shinya Itoh, Sadaaki Masuoka, Tadahiko Horiuchi, Atsushi Nakagawa, Kenju Shimogawa, Hiroyuki Takahashi

IEEE J. Solid State Circuits, 2000