Norihisa Arai

According to our database, Norihisa Arai authored at least 3 papers between 1990 and 2002.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2002

A 125-mm² 1-Gb NAND flash memory with 10-MByte/s program speed.

Kenichi Imamiya, Hiroshi Nakamura, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian J. Che

IEEE J. Solid State Circuits, 2002

1991

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique.

Naoto Tomita, Nobuaki Ohtsuka, Jun-ichi Miyamoto, Ken-ichi Imamiya, Yumiko Iyama, Seiichi Mori, Yoichi Ohshima, Norihisa Arai, Yukio Kaneko, Eiji Sakagami, Kuniyoshi Yoshikawa, Sumio Tanaka

IEEE J. Solid State Circuits, November, 1991

1990

A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design.

Kenichi Imamiya, Jun-ichi Miyamoto, Shigeru Atsumi, Nobuaki Ohtsuka, Yukinori Muroya, Toshiyuki Sako, Masao Higashino, Yumiko Iyama, Seiichi Mori, Yoichi Ohshima, Hitoshi Araki, Yukio Kaneko, Kazuhito Narita, Norihisa Arai, Kuniyoshi Yoshikawa, Shinichi Tanaka

IEEE J. Solid State Circuits, February, 1990