Noriaki Nakayama

According to our database1, Noriaki Nakayama authored at least 16 papers between 1995 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2010
Decomposition of drain-current variation into gain-factor and threshold voltage variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors.
IEEE J. Solid State Circuits, 2009

Physical design challenges to nano-CMOS circuits.
IEICE Electron. Express, 2009

2008
Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress.
IEICE Trans. Electron., 2008

An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution.
Proceedings of the 45th Design Automation Conference, 2008

Determination of optimal polynomial regression function to decompose on-die systematic and random variations.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2005
A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential.
IEICE Trans. Electron., 2005

1/<i>f</i>-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation.
IEICE Trans. Electron., 2005

2003
Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
On discrete random dopant modeling in drift-diffusion simulations: physical meaning of 'atomistic' dopants.
Microelectron. Reliab., 2002

Circuit Simulation Models for Coming MOSFET Generations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001
Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

Correlation method of circuit-performance and technology fluctuations for improved design reliability.
Proceedings of ASP-DAC 2001, 2001

1995
Numerical simulation of neuronal population coding: influences of noise and tuning width on the coding error.
Biol. Cybern., 1995


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