Noriaki Maeda
Orcid: 0000-0002-4447-8917
According to our database1,
Noriaki Maeda
authored at least 14 papers
between 2005 and 2024.
Collaborative distances:
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Bibliography
2024
Adaptation of Postural Sway in a Standing Position during Tilted Video Viewing Using Virtual Reality: A Comparison between Younger and Older Adults.
Sensors, May, 2024
Development of fall prevention training device that can provide external disturbance to the ankle with pneumatic gel muscles (PGM) while walking.
CoRR, 2024
2021
Walking Practice Combined with Virtual Reality Contributes to Early Acquisition of Symmetry Prosthetic Walking: An Experimental Study Using Simulated Prosthesis.
Symmetry, 2021
Association between the Degree of Pre-Synaptic Dopaminergic Pathway Degeneration and Motor Unit Firing Behavior in Parkinson's Disease Patients.
Sensors, 2021
Effect of Acute Static Stretching on the Activation Patterns Using High-Density Surface Electromyography of the Gastrocnemius Muscle during Ramp-Up Task.
Sensors, 2021
2014
10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor.
IEEE Micro, 2013
A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS.
IEEE J. Solid State Circuits, 2013
A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
2009
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2006
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique.
IEEE J. Solid State Circuits, 2006
2005
A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor.
IEEE J. Solid State Circuits, 2005