Noriaki Maeda

According to our database, Noriaki Maeda authored at least 13 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Adaptation of Postural Sway in a Standing Position during Tilted Video Viewing Using Virtual Reality: A Comparison between Younger and Older Adults.

Tsubasa Tashiro, Noriaki Maeda, Takeru Abekura, Rami Mizuta, Yui Terao, Satoshi Arima, Satoshi Onoue, Yukio Urabe

Sensors, May, 2024

2021

Walking Practice Combined with Virtual Reality Contributes to Early Acquisition of Symmetry Prosthetic Walking: An Experimental Study Using Simulated Prosthesis.

Kazuki Fukui, Noriaki Maeda, Makoto Komiya, Shogo Tsutsumi, Keita Harada, Sayo Kuroda, Masanori Morikawa, Yukio Urabe

Symmetry, 2021

Association between the Degree of Pre-Synaptic Dopaminergic Pathway Degeneration and Motor Unit Firing Behavior in Parkinson's Disease Patients.

Yuichi Nishikawa, Kohei Watanabe, Ales Holobar, Tetsuya Takahashi, Noriaki Maeda, Hirofumi Maruyama, Shinobu Tanaka, Allison S. Hyngstrom

Sensors, 2021

Effect of Acute Static Stretching on the Activation Patterns Using High-Density Surface Electromyography of the Gastrocnemius Muscle during Ramp-Up Task.

Noriaki Maeda, Makoto Komiya, Yuichi Nishikawa, Masanori Morikawa, Shogo Tsutsumi, Tsubasa Tashiro, Kazuki Fukui, Hiroaki Kimura, Yukio Urabe

Sensors, 2021

2014

10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores.

Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Noriaki Maeda, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor.

Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Takeshi Kataoka, Toshihiro Hattori

IEEE Micro, 2013

A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS.

Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki

IEEE J. Solid State Circuits, 2013

A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor.

Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Takeshi Kataoka, Toshihiro Hattori

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS.

Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Yasuhisa Shimazaki

Proceedings of the Symposium on VLSI Circuits, 2012

2009

A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation.

Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS.

Masanao Yamaoka, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006

90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique.

Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara

IEEE J. Solid State Circuits, 2006

2005

A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor.

Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada

IEEE J. Solid State Circuits, 2005