Norbert Wehn

Mohammad Hassani Sadi

Jannis Clausius

Stephan ten Brink

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

Artificial Neural Networks-Based Radar Remote Sensing to Estimate Geographical Information during Oil-Spills.

[BibT_eX]

[DOI]

Proceedings of the 30th European Signal Processing Conference, 2022

Machine learning based soft error rate estimation of pass transistor logic in high-speed communication.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2022

Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A Custom Hardware Architecture for the Link Assessment Problem.

[BibT_eX]

[DOI]

Proceedings of the Algorithms for Big Data - DFG Priority Program 1736, 2022

Increasing the Sampling Efficiency for the Link Assessment Problem.

[BibT_eX]

[DOI]

Proceedings of the Algorithms for Big Data - DFG Priority Program 1736, 2022

2021

Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2021

A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing.

[BibT_eX]

[DOI]

J. Imaging, 2021

iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2021

Longevity of Commodity DRAMs in Harsh Environments Through Thermoelectric Cooling.

[BibT_eX]

[DOI]

IEEE Access, 2021

Embedded Face Recognition for Personalized Services in the Assistive Robotics.

[BibT_eX]

[DOI]

Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2021

Online Working Set Change Detection with Constant Complexity: The Cornerstone for Memory Management Algorithms in Scalable Systems.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2021: The International Symposium on Memory Systems, Washington, USA, September 27, 2021

An LPDDR4 Safety Model for Automotive Applications.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2021: The International Symposium on Memory Systems, Washington, USA, September 27, 2021

Exploration of DDR5 with the Open-Source Simulator DRAMSys.

[BibT_eX]

[DOI]

Lukas Steiner

Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2021

Forward-Error-Correction for Beyond-5G Ultra-High Throughput Communications.

[BibT_eX]

[DOI]

Onur Sahin

Proceedings of the 11th International Symposium on Topics in Coding, 2021

Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Topics in Coding, 2021

Energy Efficient FEC Decoders.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Topics in Coding, 2021

Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

On the Energy Costs of Post-Quantum KEMs in TLS-based Low-Power Secure IoT.

[BibT_eX]

[DOI]

Maximilian Schöffel

Frederik Lauer

Proceedings of the IoTDI '21: International Conference on Internet-of-Things Design and Implementation, 2021

ADMM-Based ML Decoding: from Theory to Practice.

[BibT_eX]

[DOI]

Kira Kraft

Proceedings of the IEEE International Conference on Acoustics, 2021

HALF: Holistic Auto Machine Learning for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

A 336 Gbit/s Full-Parallel Window Decoder for Spatially Coupled LDPC Codes.

[BibT_eX]

[DOI]

Proceedings of the Joint European Conference on Networks and Communications & 6G Summit, 2021

QuantYOLO: A High-Throughput and Power-Efficient Object Detection Network for Resource and Power Constrained UAVs.

[BibT_eX]

[DOI]

Muhammad Gohar Javed

Minahil Raza

Proceedings of the 2021 Digital Image Computing: Techniques and Applications, 2021

Burnt Forest Estimation from Sentinel-2 Imagery of Australia using Unsupervised Deep Learning.

[BibT_eX]

[DOI]

Marcus Liwicki

Proceedings of the 2021 Digital Image Computing: Techniques and Applications, 2021

The Dynamic Random Access Memory Challenge in Embedded Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the A Journey of Embedded and Cyber-Physical Systems, 2021

A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Adaptable Approximation Based on Bit Decomposition for Deep Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2020

Efficient Hardware Architectures for 1D- and MD-LSTM Networks.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2020

A Reduced-Complexity Projection Algorithm for ADMM-Based LP Decoding.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 2020

Real-Time Energy Efficient Hand Pose Estimation: A Case Study.

[BibT_eX]

[DOI]

Mhd Rashed Al Koutayni

Sensors, 2020

Harvester-aware transient computing: Utilizing the mechanical inertia of kinetic energy harvesters for a proactive frequency-based power loss detection.

[BibT_eX]

[DOI]

Daniel Rodrigues Carvalho

Integr., 2020

The gem5 Simulator: Version 20.0+.

[BibT_eX]

[DOI]

Amin Farmahini Farahani

Hamidreza Khaleghzadeh

CoRR, 2020

Advanced Hardware Architectures for Turbo Code Decoding Beyond 100 Gb/s.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Wireless Communications and Networking Conference, 2020

A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

FERA: A Framework for Critical Assessment of Execution Monitoring Based Approaches for Finding Concurrency Bugs.

[BibT_eX]

[DOI]

Pablo Oliveira Antonino

Proceedings of the Intelligent Computing, 2020

System simulation with PULP virtual platform and SystemC.

[BibT_eX]

[DOI]

Proceedings of the RAPIDO 2020 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2020

Low-complexity Computational Units for the Local-SOVA Decoding Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE Annual International Symposium on Personal, 2020

A 506Gbit/s Polar Successive Cancellation List Decoder with CRC.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE Annual International Symposium on Personal, 2020

Efficient Generation of Application Specific Memory Controllers.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

Multi-Valued Physical Unclonable Functions based on Dynamic Random Access Memory.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

An Energy Efficient 3D-Heterogeneous Main Memory Architecture for Mobile Devices.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

Access-Aware Per-Bank DRAM Refresh for Reduced DRAM Refresh Overhead.

[BibT_eX]

[DOI]

Éder F. Zulian

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Fully Pipelined Iteration Unrolled Decoders the Road to TB/S Turbo Decoding.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network.

[BibT_eX]

[DOI]

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

TLS-Level Security for Low Power Industrial IoT Network Infrastructures.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Fast and Accurate DRAM Simulation: Can we Further Accelerate it?

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Analysis and Optimization of TLS-based Security Mechanisms for Low Power IoT Systems.

[BibT_eX]

[DOI]

Frederik Lauer

Syed Mohammad Asad Hassan Jafri

Proceedings of the 20th IEEE/ACM International Symposium on Cluster, 2020

Efficient FeFET Crossbar Accelerator for Binary Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex.

[BibT_eX]

[DOI]

CoRR, 2019

Wednesday Keynote: The Memory Wall: Challenges and Solutions.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements.

[BibT_eX]

[DOI]

Proceedings of the XVI International Symposium "Problems of Redundancy in Information and Control Systems", 2019

iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Adaptive Transient Computing for Power-Neutral Embedded Devices.

[BibT_eX]

[DOI]

Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

Fast validation of DRAM protocols with timed petri nets.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2019

An In-DRAM Neural Network Processing Engine.

[BibT_eX]

[DOI]

Chirag Sudarshan

Jan Lappas

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Rapid Identification of Shared Memory in Multithreaded Embedded Systems with Static Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 48th International Conference on Parallel Processing, 2019

Polar Code Decoder Framework.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Speculative Temporal Decoupling Using fork().

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Low-Latency CRC Calculation in Turbo-Code Decoding.

[BibT_eX]

[DOI]

Int. J. Wirel. Inf. Networks, 2018

A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs.

[BibT_eX]

[DOI]

Valentin Grigorovici

IEEE Des. Test, 2018

BOSMI: a framework for non-intrusive monitoring and testing of embedded multithreaded software on the logical level.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

A Framework for Non-intrusive Trace-driven Simulation of Manycore Architectures with Dynamic Tracing Configuration.

[BibT_eX]

[DOI]

Proceedings of the Runtime Verification - 18th International Conference, 2018

Sparsity in Deep Neural Networks - An Empirical Investigation with TensorQuant.

[BibT_eX]

[DOI]

Proceedings of the ECML PKDD 2018 Workshops, 2018

Efficient coding scheme for DDR4 memory subsystems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2018

Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2018

25 Years of Turbo Codes: From Mb/s to beyond 100 Gb/s.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

When Channel Coding Hits the Implementation Wall.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

A Low-Complexity Projection Algorithm for ADMM-Based LP Decoding.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

The Role of Memories in Transprecision Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Reconfigurable Accelerator for Morphological Operations.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Improved Maximum-Likelihood Decoding Using Sparse Parity-Check Matrices.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Telecommunications, 2018

FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs.

[BibT_eX]

[DOI]

Alessandro Pappalardo

Giulio Gambardella

Michaela Blott

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing: Percentile Based Binarization.

[BibT_eX]

[DOI]

Syed Saqib Bukhari

Aqib Ghafoor

Proceedings of the ACM Symposium on Document Engineering 2018, 2018

An analysis on retention error behavior and power consumption of recent DDR4 DRAMs.

[BibT_eX]

[DOI]

Deepak M. Mathew

Martin Schultheis

Dimitrios S. Nikolopoulos

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

The transprecision computing paradigm: Concept, design, and applications.

[BibT_eX]

[DOI]

A. Cristiano I. Malossi

Eric Flamand

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improving the error behavior of DRAM by exploiting its Z-channel property.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2017

DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2017

3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2017

A Platform to Analyze DDR3 DRAM's Power and Retention Time.

[BibT_eX]

[DOI]

Deepak M. Mathew

IEEE Des. Test, 2017

The memory challenge in computing systems: A survey.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Advanced wireless digital baseband signal processing beyond 100 Gbit/s.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Real-Time Financial Risk Measurement of Dynamic Complex Portfolios with Python and PyOpenCL.

[BibT_eX]

[DOI]

Sascha Desmettre

Proceedings of the 7th Workshop on Python for High-Performance and Scientific Computing, 2017

TensorQuant: A Simulation Toolbox for Deep Neural Network Quantization.

[BibT_eX]

[DOI]

Proceedings of the Machine Learning on HPC Environments, 2017

System simulation with gem5 and SystemC: The keystone for full interoperability.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Supervised testing of concurrent software in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

A new state model for DRAMs using Petri Nets.

[BibT_eX]

[DOI]

Kira Kraft

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

A Bank-Wise DRAM Power Model for System Simulations.

[BibT_eX]

[DOI]

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2017

Using run-time reverse-engineering to optimize DRAM refresh.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2017

Integrating DRAM power-down modes in gem5 and quantifying their impact.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2017

Near Real-Time Risk Simulation of Complex Portfolios on Heterogeneous Computing Systems with OpenCL.

[BibT_eX]

[DOI]

Proceedings of the 5th International Workshop on OpenCL, 2017

Exploiting Decoupled OpenCL Work-Items with Data Dependencies on FPGAs: A Case Study.

[BibT_eX]

[DOI]

Qian Liang

Songyin Tang

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Enhanced decoding for high-rate LTE Turbo-Codes with short block lengths.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Communications Workshops, 2017

An advanced embedded architecture for connected component analysis in industrial applications.

[BibT_eX]

[DOI]

Menbere Tekleyohannes

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Hardware architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character Recognition.

[BibT_eX]

[DOI]

Mohammad Reza Yousefi

Didier Stricker

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

A Wearable Flexible Sensor Network Platform for the Analysis of Different Sport Movements.

[BibT_eX]

[DOI]

Proceedings of the Advances in Human Factors in Wearable Technologies and Game Design, 2017

Bit-level pipelining for highly parallel turbo-code decoders: A critical assessment.

[BibT_eX]

[DOI]

Kira Kraft

Proceedings of the IEEE AFRICON 2017, Cape Town, South Africa, September 18-20, 2017, 2017

2016

Increasing sampling efficiency for the fixed degree sequence model with phase transitions.

[BibT_eX]

[DOI]

Alexandre Flores John

Wolfgang Eugen Schlauch

Soc. Netw. Anal. Min., 2016

A cross layer approach for efficient thermal management in 3D stacked SoCs.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

Precision-tuning and hybrid pricer for closed-form solution-based Heston calibration.

[BibT_eX]

[DOI]

Gongda Liu

Concurr. Comput. Pract. Exp., 2016

A New Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256).

[BibT_eX]

[DOI]

Proceedings of the IEEE 83rd Vehicular Technology Conference, 2016

Exploring system performance using elastic traces: Fast, accurate and portable.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

A new bank sensitive DRAMPower model for efficient design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Reverse Engineering of DRAMs: Row Hammer with Crosshair.

[BibT_eX]

[DOI]

Proceedings of the Second International Symposium on Memory Systems, 2016

ConGen: An Application Specific DRAM Memory Controller Generator.

[BibT_eX]

[DOI]

Proceedings of the Second International Symposium on Memory Systems, 2016

On the applicability of trellis compression to Turbo-Code decoder hardware architectures.

[BibT_eX]

[DOI]

Frederic Pohl

Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

Advanced iterative channel coding schemes: When Shannon meets Moore.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

ADMM versus simplex algorithm for LP decoding.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

Precise synchronization time stamp generation for Bluetooth low energy.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016

IMU-based determination of fatigue during long sprint.

[BibT_eX]

[DOI]

Marcus Schmidt

Sebastian Wille

Thomas Jaitner

Proceedings of the 2016 ACM International Joint Conference on Pervasive and Ubiquitous Computing and Proceedings of the 2016 ACM International Symposium on Wearable Computers, 2016

Saturated min-sum decoding: An "afterburner" for LDPC decoder hardware.

[BibT_eX]

[DOI]

Daniel Müller-Gritschneder

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Error resilience and energy efficiency: An LDPC decoder design study.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Efficient reliability management in SoCs - an approximate DRAM perspective.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Application-aware cross-layer reliability analysis and optimization.

[BibT_eX]

[DOI]

Fabian Oboril

Ulf Schlichtmann

Mehdi Baradaran Tahoori

Jürgen Teich

it Inf. Technol., 2015

DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2015

Optimization strategies for portable code for Monte Carlo-based value-at-risk systems.

[BibT_eX]

[DOI]

Sascha Desmettre

Proceedings of the 8th Workshop on High Performance Computational Finance, 2015

A high-level DRAM timing, power and area exploration tool.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Exploiting the brownian bridge technique to improve longstaff-schwartz american option pricing on FPGA systems.

[BibT_eX]

[DOI]

Songyin Tang

Steffen Omland

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Latency reduction for LTE/LTE-A turbo-code decoders by on-the-fly calculation of CRC.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Personal, 2015

A new architecture for high throughput, low latency NB-LDPC check node processing.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Personal, 2015

Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Symposium on Memory Systems, 2015

Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Custom Computing System for Finding Similarties in Complex Networks.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Syndrome based check node processing of high order NB-LDPC decoders.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Telecommunications, 2015

Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Reverse longstaff-schwartz american option pricing on hybrid CPU/FPGA systems.

[BibT_eX]

[DOI]

Songyin Tang

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Exploiting Phase Transitions for the Efficient Sampling of the Fixed Degree Sequence Model.

[BibT_eX]

[DOI]

Alexandre Flores John

Andreas Spitz

Proceedings of the 2015 IEEE/ACM International Conference on Advances in Social Networks Analysis and Mining, 2015

2014

A Cross-Layer Reliability Design Methodology for Efficient, Dependable Wireless Receivers.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

Reliability analysis of MIMO channel preprocessing by fault injection.

[BibT_eX]

[DOI]

Victor Tomashevich

Ilia Polian

Proceedings of the 2014 IEEE International Conference on Wireless for Space and Extreme Environments, 2014

Optimized active and power-down mode refresh control in 3D-DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

A systematic methodology for analyzing closed-form Heston pricer regarding their accuracy and runtime.

[BibT_eX]

[DOI]

Gongda Liu

Proceedings of the 7th Workshop on High Performance Computational Finance, 2014

A simplex algorithm for LP decoding hardware.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Annual International Symposium on Personal, 2014

Advanced hardware architecture for soft decoding Reed-Solomon codes.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Turbo Codes and Iterative Information Processing, 2014

A Wearable Inertial Sensor Unit for Jump Diagnosis in Multiple Athletes.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Congress on Sports Sciences Research and Technology Support, 2014

Monitoring household activities and user location with a cheap, unobtrusive thermal sensor array.

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM International Joint Conference on Pervasive and Ubiquitous Computing, 2014

HyPER: A runtime reconfigurable architecture for monte carlo option pricing in the Heston model.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems.

[BibT_eX]

[DOI]

Victor Tomashevich

Christian Fesl

Ilia Polian

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Hardware implementation of a Reed-Solomon soft decoder based on information set decoding.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Connecting different worlds - Technology abstraction for reliability-aware design and Test.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Technology transfer towards Horizon 2020.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Exploiting expendable process-margins in DRAMs for run-time performance optimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Feedforward carrier synchronization for pilotless bursts of DVB-RCS2.

[BibT_eX]

[DOI]

Imran Ali

Uwe Wasenmüller

Proceedings of the 9th International Symposium on Communication Systems, 2014

Mixed precision multilevel Monte Carlo on hybrid computing systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Computational Intelligence for Financial Engineering & Economics, 2014

2013

Exploration and Optimization of 3-D Integrated DRAM Subsystems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Performance evaluation of ambient services by combining robotic frameworks and a smart environment platform.

[BibT_eX]

[DOI]

Robotics Auton. Syst., 2013

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience.

[BibT_eX]

[DOI]

Veit Kleeberger

Daniel Mueller-Gritschneder

Andreas Herkersdorf

Sani R. Nassif

Ulf Schlichtmann

IEEE Micro, 2013

Cross-Layer Error Resilience and Its Application to Wireless Communication Systems.

[BibT_eX]

[DOI]

J. Low Power Electron., 2013

A new dimension of parallelism in ultra high throughput LDPC decoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Loopy - An open-source TCP/IP rapid prototyping and validation framework.

[BibT_eX]

[DOI]

Thomas Fischer

Arnd Poetzsch-Heffter

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2013

ASIC implementation of a modified QR decomposition for tree search based MIMO detection.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Activity recognition and nutrition monitoring in every day situations with a textile capacitive neckband.

[BibT_eX]

[DOI]

Jingyuan Cheng

Bo Zhou

Kai Kunze

Proceedings of the 2013 ACM International Joint Conference on Pervasive and Ubiquitous Computing, 2013

Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ.

[BibT_eX]

[DOI]

Proceedings of the 10th FPGAworld Conference, 2013

A multi-level Monte Carlo FPGA accelerator for option pricing in the Heston model.

[BibT_eX]

[DOI]

Pedro Torruella

Proceedings of the Design, Automation and Test in Europe, 2013

System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Reliable on-chip systems in the nano-era: lessons learnt and future trends.

[BibT_eX]

[DOI]

Mehdi Baradaran Tahoori

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Towards variation-aware system-level power estimation of DRAMs: an empirical approach.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Code-aided synchronization with QPSK, 8-PSK and 16-QAM modulations.

[BibT_eX]

[DOI]

Imran Ali

Uwe Wasenmüller

Proceedings of the 19th Asia-Pacific Conference on Communications, 2013

Hardware implementations of Gaussian elimination over GF(2) for channel decoding algorithms.

[BibT_eX]

[DOI]

Christopher Stumm

Proceedings of the AFRICON 2013, Pointe aux Piments, Mauritius, September 9-12, 2013, 2013

2012

Design Space of Flexible Multigigabit LDPC Decoders.

[BibT_eX]

[DOI]

VLSI Design, 2012

A Hardware Efficient Random Number Generator for Nonuniform Distributions with Arbitrary Precision.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2012

Reliability study on system memories of an iterative MIMO-BICM system.

[BibT_eX]

[DOI]

Christian Brehm

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

FPGA-based rapid prototyping platform for MIMO-BICM design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

A 2.15GBit/s turbo code decoder for LTE advanced base station applications.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

A High-Performance FPGA-Based Implementation of the LZSS Compression Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

ASIC design of a Gbit/s LDPC decoder for iterative MIMO systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computing, Networking and Communications, 2012

Combining robotic frameworks with a smart environment framework: MCA2/SimVis3D and TinySEP.

[BibT_eX]

[DOI]

Proceedings of the 2012 ACM Conference on Ubiquitous Computing, 2012

Dependable embedded systems: The German research foundation DFG priority program SPP 1500.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

A Parallel Adaptive Range Coding Compressor: Algorithm, FPGA Prototype, Evaluation.

[BibT_eX]

[DOI]

Proceedings of the 2012 Data Compression Conference, Snowbird, UT, USA, April 10-12, 2012, 2012

An energy efficient DRAM subsystem for 3D integrated SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

DRAM selection and configuration for real-time mobile systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A Case Study on Error Resilient Architectures for Wireless Communication.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

2011

On Complexity, Energy- and Implementation-Efficiency of Channel Decoders.

[BibT_eX]

[DOI]

Heinrich Meyr

IEEE Trans. Commun., 2011

A monolithic LTE interleaver generator for highly parallel SMAP decoders.

[BibT_eX]

[DOI]

Thomas Ilnseher

Proceedings of the 2011 Wireless Telecommunications Symposium, 2011

Algorithmic complexity in the heston model: an implementation view.

[BibT_eX]

[DOI]

Henning Marxen

Anton Kostiuk

Stephan Wurm

Proceedings of the WHPCF'11, 2011

Validation of channel decoding ASIPs a case study.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

An Energy Efficient FPGA Accelerator for Monte Carlo Option Pricing with the Heston Model.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Energy Efficient Acceleration and Evaluation of Financial Computations towards Real-Time Pricing.

[BibT_eX]

[DOI]

Proceedings of the Knowledge-Based and Intelligent Information and Engineering Systems, 2011

A scalable multi-ASIP architecture for standard compliant trellis decoding.

[BibT_eX]

[DOI]

Christian Brehm

Thomas Ilnseher

Proceedings of the International SoC Design Conference, 2011

Bringing C++ productivity to VHDL world: From language definition to a case study.

[BibT_eX]

[DOI]

Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Design space exploration for 3D-stacked DRAMs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Design and architectures for dependable embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Reliability: A Cross-Disciplinary and Cross-Layer Approach.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

A separation algorithm for improved LP-decoding of linear block codes.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 2010

Implementation comparisons of the QR decomposition for MIMO detection.

[BibT_eX]

[DOI]

Gabriel Luca Nazar

Christina Gimmler

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

A New Hardware Efficient Inversion Based Random Number Generator for Non-uniform Distributions.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Low-complexity iteration control for MIMO-BICM systems.

[BibT_eX]

[DOI]

Christina Gimmler

Timo Lehnigk-Emden

Proceedings of the IEEE 21st International Symposium on Personal, 2010

AmICA - A Flexible, Compact, Easy-to-Program and Low-Power WSN Platform.

[BibT_eX]

[DOI]

Proceedings of the Mobile and Ubiquitous Systems: Computing, Networking, and Services, 2010

A 477mW NoC-based digital baseband for MIMO 4G SDR.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Fully integrated UWB impulse transmitter and 402-to-405MHz super-regenerative receiver for medical implant devices.

[BibT_eX]

[DOI]

Maurits Ortmanns

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Complete Verification of Weakly Programmable IPs against Their Operational ISA Model.

[BibT_eX]

Proceedings of the 2010 Forum on specification & Design Languages, 2010

RF spectrum sensing technique for cognitive UWB radio network.

[BibT_eX]

[DOI]

Maurits Ortmanns

Proceedings of the 36th European Solid-State Circuits Conference, 2010

A rapid prototyping system for error-resilient multi-processor systems-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

A 150Mbit/s 3GPP LTE Turbo code decoder.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems.

[BibT_eX]

[DOI]

Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009

Energy simulation of embedded XScale systems with XEEMU.

[BibT_eX]

[DOI]

J. Embed. Comput., 2009

DRAM power management and energy consumption: a critical assessment.

[BibT_eX]

[DOI]

Daniel Schmidt

Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Valid inequalities for binary linear codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Information Theory, 2009

A novel LDPC decoder for DVB-S2 IP.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Error correction in single-hop wireless sensor networks - A case study.

[BibT_eX]

[DOI]

Daniel Schmidt

Matthias Berning

Proceedings of the Design, Automation and Test in Europe, 2009

2008

A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Designing efficient irregular networks for heterogeneous systems-on-chip.

[BibT_eX]

[DOI]

J. Syst. Archit., 2008

Macro Interleaver Design for Bit Interleaved Coded Modulation with Low-Density Parity-Check Codes.

[BibT_eX]

[DOI]

Proceedings of the 67th IEEE Vehicular Technology Conference, 2008

Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Fully integrated self-quenched super-regenerative UWB impulse detector.

[BibT_eX]

[DOI]

Reinhard Tielert

Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008

3.1-to-7GHz UWB impulse radio transceiver front-end based on statistical correlation technique.

[BibT_eX]

[DOI]

Reinhard Tielert

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Application-specific reconfigurable processors.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Super-regenerative UWB impulse detector with synchronized quenching mechanism.

[BibT_eX]

[DOI]

Reinhard Tielert

Proceedings of the ESSCIRC 2008, 2008

A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder.

[BibT_eX]

[DOI]

Matthias Alles

Proceedings of the Design, Automation and Test in Europe, 2008

Cognitive Radio Prototyping.

[BibT_eX]

[DOI]

Rafael Rodriguez Velilla

Proceedings of the 3rd International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2008

2007

A Survey on LDPC Codes and Decoders for OFDM-based UWB Systems.

[BibT_eX]

[DOI]

Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

A Reliability-Aware LDPC Code Decoding Algorithm.

[BibT_eX]

[DOI]

Matthias Alles

Torben Brack

Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

Implementation Issues of Turbo Synchronization with Duo-Binary Turbo Decoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE 18th International Symposium on Personal, 2007

XEEMU: An Improved XScale Power Simulator.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Evaluation of High Throughput Turbo-Decoder Architectures.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Low complexity LDPC code decoders for next generation standards.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Fast convergence algorithm for LDPC Codes.

[BibT_eX]

[DOI]

Timo Lehnigk-Emden

Proceedings of the 63rd IEEE Vehicular Technology Conference, 2006

A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

A Reconfigurable Multi-Processor Platform for Convolutional and Turbo Decoding.

[BibT_eX]

Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE 17th International Symposium on Personal, 2006

Advanced Channel Decoding Algorithms and Their Implementation for Future Communication Systems.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Disclosing the LDPC code decoder design space.

[BibT_eX]

[DOI]

Torben Brack

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A Reconfigurable Outer Modem Platform for Future Communications Systems.

[BibT_eX]

[DOI]

Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

2005

A Scalable System Architecture for High-Throughput Turbo-Decoders.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2005

Architecture-driven voltage scaling for high-throughput turbo-decoders.

[BibT_eX]

[DOI]

J. Embed. Comput., 2005

Network-on-chip-centric approach to interleaving in high throughput channel decoders.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Energieminimierung von Basisbandsignalverarbeitungsalgorithmen auf programmierbaren Plattformen.

[BibT_eX]

[DOI]

Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

A Synthesizable IP Core for DVB-S2 LDPC Code Decoding.

[BibT_eX]

[DOI]

Torben Brack

Proceedings of the 2005 Design, 2005

Power Optimization in advanced Channel Coding.

[BibT_eX]

[DOI]

Proceedings of the Power-aware Computing Systems, 3.-8. April 2005, 2005

2004

A multi-standard channel-decoder for base-station applications.

[BibT_eX]

[DOI]

Philippe Alves

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

FPGA implementation of parallel turbo-decoders.

[BibT_eX]

[DOI]

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications.

[BibT_eX]

[DOI]

Armin Wellig

Julien Zory

Proceedings of the Integrated Circuit and System Design, 2004

Joint graph-decoder design of IRA codes on scalable architectures [LDPC codes].

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Channel Decoder Architecture for 3G Mobile Wireless Terminals.

[BibT_eX]

[DOI]

Friedbert Berens

Gerd Kreiselmaier

Proceedings of the 2004 Design, 2004

Design methodology for IRA codes.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Vergleich von Hardware- und Software-Implementierungen in der digitalen Kommunikation am Beispiel der Kanalcodierung (Hardware-/Software Trade-Offs in Digital Communication Systems with Special Emphasis on Channel-Coding).

[BibT_eX]

[DOI]

it Inf. Technol., 2003

System-on-Chip - Ein Sonderheft anlässlich des 60. Geburtstages von Prof. Dr. Dr. h.c. mult. Manfred Glesner.

[BibT_eX]

[DOI]

it Inf. Technol., 2003

Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

Concurrent interleaving architectures for high-throughput channel coding.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

VLSI-implementation issues of turbo trellis-coded modulation.

[BibT_eX]

[DOI]

Gerd Kreiselmaier

Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors .

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

Combined Turbo and Convolutional Decoder Architecture for UMTS Wireless Applications.

[BibT_eX]

[DOI]

Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Enabling high-speed turbo-decoding through concurrent interleaving.

[BibT_eX]

[DOI]

L. P. Rao

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Optimized concurrent interleaving architecture for high-throughput turbo-decoding.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Evaluation of algorithm optimizations for low-power Turbo-Decoder implementations.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2002

Hardware/Software Trade-Offs for Advanced 3G Channel Coding.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

Turbo-decoder quantization for UMTS.

[BibT_eX]

[DOI]

Heiko Michel

IEEE Commun. Lett., 2001

Embedded DRAM Development: Technology, Physical Design, and Application Issues.

[BibT_eX]

[DOI]

Doris Keitel-Schulz

IEEE Des. Test Comput., 2001

Vlsi Architectures For High-Speed Map Decoders.

[BibT_eX]

[DOI]

Holger Lamm

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Embedded Memories in System Design: Technology, Application, Design and Tools.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Design of low-power high-speed maximum a priori decoder architectures.

[BibT_eX]

[DOI]

Holger Lamm

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Low power implementation of a turbo-decoder on programmable architectures.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

Turbo-decoding without SNR estimation.

[BibT_eX]

[DOI]

Peter A. Hoeher

IEEE Commun. Lett., 2000

Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

1998

Issues in Embedded DRAM Development and Applications.

[BibT_eX]

[DOI]

Doris Keitel-Schulz

Proceedings of the 11th International Symposium on System Synthesis, 1998

Embedded DRAM Architectural Trade-Offs.

[BibT_eX]

[DOI]

Søren Hein

Proceedings of the 1998 Design, 1998

1997

An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions.

[BibT_eX]

[DOI]

Michael Münch

ACM Trans. Design Autom. Electr. Syst., 1997

1995

Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

1994

The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1994

Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization.

[BibT_eX]

[DOI]

Bernd Wurth

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Scheduling of behavioral VHDL by retiming techniques.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

1993

The Siemens high-level synthesis system CALLAS.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1993

Estimating lower hardware bounds in high-level synthesis.

[BibT_eX]

C. Vielhauer

Proceedings of the VLSI 93, 1993

Synthesis of complex VHDL operators.

[BibT_eX]

[DOI]

Michael Gasteier

Proceedings of the European Design Automation Conference 1993, 1993

1992

Data Part Optimizations in the CALLAS Synthesis Environment.

[BibT_eX]

Proceedings of the Synthesis for Control Dominated Circuits, 1992

High-level synthesis in a rapid-prototype environment for mechatronic systems.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

1991

A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment.

[BibT_eX]

Jörg Biesenack

Michael Pilsl

Proceedings of the VLSI 91, 1991

A VLSI System Design for the Control of High Performance Combustion Engines.

[BibT_eX]

A. Laudenbach

Proceedings of the VLSI 91, 1991

Verifikation mikroelektronischer Systeme zur Prozeßsteuerung durch schnelle Prototypenrealisierung.

[BibT_eX]

Hans-Jürgen Herpel

Proceedings of the 7. Symposium Simulationstechnik: Fortschritte in der Simulationstechnik, 1991

RAMSES-a rapid prototyping environment for embedded control applications.

[BibT_eX]

[DOI]

Hans-Jürgen Herpel

Proceedings of the Second International Workshop on Rapid System Prototyping, 1991

A new approach to timing driven partitioning of combinational logic.

[BibT_eX]

[DOI]

Proceedings of the First Great Lakes Symposium on VLSI, 1991

HADES-high-level architecture development and exploration system.

[BibT_eX]

[DOI]

Proceedings of the First Great Lakes Symposium on VLSI, 1991

1990

Timing Driven Partitioning of Combinational Logic.

[BibT_eX]

[DOI]

Proceedings of the Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1990

1989

Effiziente Verfahren für den physikalischen Entwurf von MOS-VLSI-Schaltungen und ihre Anwendung beim Entwurf eines defekttoleranten Mikroprozessors.

[BibT_eX]

[DOI]

PhD thesis, 1989

1988

A Defect-Tolerant and Fully Testable PLA.

[BibT_eX]

[DOI]

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

The ALGIC Silicon Compiler System: Implementation, Design Experience and Results.

[BibT_eX]

[DOI]

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986

Statische und dynamische CMOS-Schaltungstechniken im Vergleich.

[BibT_eX]

[DOI]