Nohpill Park

Orcid: 0000-0003-1669-6148

According to our database1, Nohpill Park authored at least 97 papers between 1996 and 2024.

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Bibliography

2024
A non-fungible token (NFT) chain model and performance study.
Clust. Comput., July, 2024

2023
Performance modeling and analysis of Hyperledger Fabric.
Clust. Comput., October, 2023

An Asynchronous Chain and A Variable Bulk Arrival and Asynchronous Bulk Service Model.
Proceedings of the 5th ACM International Symposium on Blockchain and Secure Critical Infrastructure, 2023

An Adaptive Blockchain-Based Decentralized Network Computing and Performance Analysis.
Proceedings of the Fifth International Conference on Blockchain Computing and Applications, 2023

A Real-Time Performance Model for NFT Chains.
Proceedings of the Fifth International Conference on Blockchain Computing and Applications, 2023

2022
A Bivariate Performance Model across On- and Off-Chain in A NFT (Non-Fungible Token) Chain.
Proceedings of the Fourth International Conference on Blockchain Computing and Applications, 2022

Performance Modeling and Assurance for Cross Chain.
Proceedings of the Fourth International Conference on Blockchain Computing and Applications, 2022

2021
A Queueing Model for Industrial Public Blockchains and Validation.
Proceedings of the 22nd IEEE International Conference on Industrial Technology, 2021

A Hybrid Chain and A Double-Tuple Variable Bulk Arrival and Static Bulk Service Model.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2021

Distributed Decentralized Chain (DDC) and k-Queue Variable Bulk Arrival and Static Bulk Service Model.
Proceedings of the BSCI '21: Proceedings of the 3rd ACM International Symposium on Blockchain and Secure Critical Infrastructure, 2021

Hyperledger Fabric Node Types and Performance Study.
Proceedings of the Third International Conference on Blockchain Computing and Applications, 2021

2020
Transaction sampling algorithms for real-time crypto block dependability.
Int. J. Big Data Intell., 2020

A Variable Bulk Arrival and Static Bulk Service Queueing Model for Blockchain.
Proceedings of the BSCI '20: Proceedings of the 2nd ACM International Symposium on Blockchain and Secure Critical Infrastructure, 2020

Slim Chain and Dependability.
Proceedings of the BSCI '20: Proceedings of the 2nd ACM International Symposium on Blockchain and Secure Critical Infrastructure, 2020

Hybrid Chain And Dependability.
Proceedings of the BSCI '20: Proceedings of the 2nd ACM International Symposium on Blockchain and Secure Critical Infrastructure, 2020

2019
Availability modelling and assurance for a big data computing.
Int. J. Big Data Intell., 2019

Dependable Industrial Crypto Computing.
Proceedings of the 28th IEEE International Symposium on Industrial Electronics, 2019

2018
The Dependability of Crypto Linked Off-chain File Systems in Backend Blockchain Analytics Engine.
Int. J. Networked Distributed Comput., 2018

Optimized Common Parameter Set Extraction Framework by Multiple Benchmarking Applications on a Big Data Platform.
Int. J. Networked Distributed Comput., 2018

Optimized Common Parameter Set Extraction by Benchmarking Applications on a Big Data Platform.
Proceedings of the 19th IEEE/ACIS International Conference on Software Engineering, 2018

2017
Availability Modeling and Assurance of Map-Reduce Computing.
Proceedings of the 15th IEEE Intl Conf on Dependable, 2017

A Study of Heuristically-Based Parametric Performance Improvement/Optimization Algorithms for BigData Computing.
Proceedings of the 4th Intl Conf on Applied Computing and Information Technology/3rd Intl Conf on Computational Science/Intelligence and Applied Informatics/1st Intl Conf on Big Data, 2017

Big Streaming Data Buffering Optimization.
Proceedings of the 4th Intl Conf on Applied Computing and Information Technology/3rd Intl Conf on Computational Science/Intelligence and Applied Informatics/1st Intl Conf on Big Data, 2017

2015
Performance evaluation and tuning for MapReduce computing in Hadoop distributed file system.
Proceedings of the 13th IEEE International Conference on Industrial Informatics, 2015

Identification of the Optimal Hadoop Configuration Parameters Set for Mapreduce Computing.
Proceedings of the 3rd International Conference on Applied Computing and Information Technology, 2015

A Concordance Based Comparison of Dow Jones Industrial Average Charts.
Proceedings of the 3rd International Conference on Applied Computing and Information Technology, 2015

2014
Dynamic data rebalancing in Hadoop.
Proceedings of the 2014 IEEE/ACIS 13th International Conference on Computer and Information Science, 2014

2013
Modeling and analysis of repair and maintenance processes in Fault Tolerant Systems.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
Performance Analysis of Hybrid Forecasting Model In Stock Market Forecasting
CoRR, 2012

On the multiple fault detection of a nano crossbar.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Modeling Yield of Self-Healing Carbon Nanotubes/Silicon-Nanowire FET-based Nanoarray.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010
Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic Design.
IEEE Trans. Instrum. Meas., 2010

An Extraction Method of Lip Movement Images from Successive Image Frames in the Speech Activity Extraction Process.
Proceedings of the Entertainment Computing - ICEC 2010, 9th International Conference, 2010

A New Approach for Time Series Forecasting based on Genetic Algorithm.
Proceedings of the ISCA 23rd International Conference on Computer Applications in Industry and Engineering, 2010

2009
Introduction to the Special Section on Nanocircuits and Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2009

A Floorprint-Based Defect Tolerance for Nano-Scale Application-Specific IC.
IEEE Trans. Instrum. Meas., 2009

2008
A Probabilistic Risk Estimation with Multiple Regression Dependent Dummy Variable Method using Logit Transformation.
Proceedings of the 2008 International Conference on Modeling, 2008

Modeling and Evaluation of Threshold Defect Tolerance.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Cost-Driven Optimization of Coverage of Combined Built-In Self-Test/Automated Test Equipment Testing.
IEEE Trans. Instrum. Meas., 2007

Designing layout-timing independent quantum-dot cellular automata (QCA) circuits by global asynchrony.
J. Syst. Archit., 2007

Leakage Minimization Technique for Nanoscale CMOS VLSI.
IEEE Des. Test Comput., 2007

2006
Exploratory Data Analysis with Bivariate Dependence Functions.
Proceedings of the 2006 International Conference on Modeling, 2006

Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
Environmental-based characterization of SoC-based instrumentation systems for stratified testing.
IEEE Trans. Instrum. Meas., 2005

Reliability measurement of mass storage system for onboard instrumentation.
IEEE Trans. Instrum. Meas., 2005

Logic Restructuring for Delay Balancing in Wave-Pipelined Circuits: An Integer Programming Approach.
Proceedings of the Seventh International Symposium on Symbolic and Numeric Algorithms for Scientific Computing (SYNASC 2005), 2005

Teaching Nanotechnology by Introducing Crossbar-Based Architecture and Quantum-Dot Cellular Automata.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

QCA-Based Majority Gate Design under Radius of Effect-Induced Faults.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

An Approach to Protection Using a Non-Persistent Client-Side Page Proxy.
Proceedings of the 20th International Conference on Computers and Their Applications, 2005

2004
Sequential diagnosis of processor array systems.
IEEE Trans. Reliab., 2004

Evaluating the repair of system-on-chip (SoC) using connectivity.
IEEE Trans. Instrum. Meas., 2004

Testing Layered Interconnection Networks.
IEEE Trans. Computers, 2004

Balanced dual-stage repair for dependable embedded memory cores.
J. Syst. Archit., 2004

Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with h-hot Addressing Scheme.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Reliability Modeling and Assurance of Clockless Wave Pipeline.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Fault tolerant clockless wave pipeline design.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
Maximal diagnosis of interconnects of random access memories.
IEEE Trans. Reliab., 2003

Guest Editorial.
IEEE Trans. Instrum. Meas., 2003

Modeling and analysis of soft-test/repair for CCD-based digital X-ray systems.
IEEE Trans. Instrum. Meas., 2003

Modeling and analysis of fault tolerant multistage interconnection networks.
IEEE Trans. Instrum. Meas., 2003

Predicting Defect-Tolerant Yield in the Embedded Core Context.
IEEE Trans. Computers, 2003

Parallel testing of multi-port static random access memories.
Microelectron. J., 2003

Hardware/Software Co-Reliability of Field Reconfigurable Multi-Processor-Memory Systems with Redundant Bus.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems.
Proceedings of the 2nd IEEE International Symposium on Network Computing and Applications (NCA 2003), 2003

Optimal Spare Utilization in Repairable and Reliable Memory Cores.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

Need For Undergraduate And Graduate-Level Education In Testing Of Microelectronic Circuits And Systems.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Modeling and Evaluation of the Interconnection-driven Repairability for Distributed Embedded Memory Cores on Chip.
Proceedings of the 22nd IASTED International Conference on Modelling, 2003

Regressive Testing for System-on-Chip with Unknown-Good-Yield.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Multi-node Failure Detection and Recovery in a Pipeline Cluster.
Proceedings of the ISCA 16th International Conference on Parallel and Distributed Computing Systems, 2003

Performance Modeling and Analysis of Distributed Web Server (DWS) System with Access Frequency Distribution (AFD).
Proceedings of the ISCA 16th International Conference on Parallel and Distributed Computing Systems, 2003

2002
Analysis of stratified testing for multichip module systems.
IEEE Trans. Reliab., 2002

Quality enhancement of reconfigurable multichip module systems by redundancy utilization.
IEEE Trans. Instrum. Meas., 2002

Dynamic yield analysis and enhancement of FPGA reconfigurable memory systems.
IEEE Trans. Instrum. Meas., 2002

Quality-effective repair of multichip module systems.
J. Syst. Archit., 2002

Hardware/Software Co-Reliability of Configurable Digital Systems.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

Clustering with Mobile Agents.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

A Fault Tolerant Pipelined Cluster Model.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

Hardware-Software Co-Reliability in Field Reconfigurable Multi-Processor-Memory Systems.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Testing Layered Interconnection Networks.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

A Test-Vector Generation Methodology for Crosstalk Noise Faults.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Repairability Evaluation of Embedded Multiple Region DRAMs.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Testing and evaluating the quality-level of stratified multichip module instrumentation.
IEEE Trans. Instrum. Meas., 2001

Modeling the Dependability of N-Modular Redundancy on Demand under Malicious Agreement.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

Connectivity-Based Multichip Module Repair.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

Dependability under Malicious Agreement in N-modular Redundancy-on-Demand Systems.
Proceedings of the IEEE International Symposium on Network Computing and Applications (NCA 2001), 2001

Novel Approaches for Fault Detection in Two-Dimensional Combinational Arrays.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Testing the Configurability of Dynamic FPGAs.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999
Design Verification of FPGA Implementations.
IEEE Des. Test Comput., 1999

Stratified Testing of Multichip Module Systems under Uneven Known-Good-Yield.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1997
An Efficient Multi-Way Algorithm for Balanced Partitioning of VLSI Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Testing of programmable logic devices (PLD) with faulty resources.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996
Conformance Testing of Time-Dependent Protocols.
Proceedings of the 2nd IEEE International Conference on Engineering of Complex Computer Systems (ICECCS '96), 1996

Space Cutting Approaches for Repairing Memories.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Modeling Quality Reduction of Multichip Module Systems due to Uneven Fault-Coverage and Imperfect Diagnosis.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996


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