Noel Menezes

According to our database, Noel Menezes authored at least 25 papers between 1993 and 2019.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2019

Session details: Keynote.

Noel Menezes

Proceedings of the 2019 International Symposium on Physical Design, 2019

2008

A "true" electrical cell model for timing, noise, and power grid verification.

Noel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin

Proceedings of the 45th Design Automation Conference, 2008

2007

A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis.

Farid N. Najm, Noel Menezes, Imad A. Ferzli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

The good, the bad, and the statistical.

Noel Menezes

Proceedings of the 2007 International Symposium on Physical Design, 2007

A nonlinear cell macromodel for digital applications.

Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Comparative Analysis of Conventional and Statistical Design Techniques.

Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De

Proceedings of the 44th Design Automation Conference, 2007

2006

A multi-port current source model for multiple-input switching effects in CMOS library cells.

Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout

Proceedings of the 43rd Design Automation Conference, 2006

2005

Variability modeling and variability-aware design in deep submicron integrated circuits.

Florentin Dartu, Anirudh Devgan, Noel Menezes

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Statistical static timing analysis: how simple can we get?

Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail

Proceedings of the 42nd Design Automation Conference, 2005

2004

Repeater scaling and its impact on CAD.

Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Statistical timing analysis based on a timing yield model.

Farid N. Najm, Noel Menezes

Proceedings of the 41th Design Automation Conference, 2004

2003

The scaling challenge: can correct-by-construction design help?

Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick

Proceedings of the 2003 International Symposium on Physical Design, 2003

2001

Optimization and Analysis Techniques for the Deep Submicron Regime.

Noel Menezes, Sachin S. Sapatnekar

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

1999

Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect.

Noel Menezes, Chung-Ping Chen

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching.

Chung-Ping Chen, Noel Menezes

Proceedings of the 36th Conference on Design Automation, 1999

1997

Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets.

Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

A sequential quadratic programming approach to concurrent gate and wire sizing.

Noel Menezes, Ross Baldick, Lawrence T. Pileggi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Clustering and Load Balancing for Buffered Clock Tree Synthesis.

Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996

Post-processing of clock trees via wiresizing and buffering for robust design.

Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Performance computation for precharacterized CMOS gates with RC loads.

Florentin Dartu, Noel Menezes, Lawrence T. Pileggi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization.

Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi

Proceedings of the 32st Conference on Design Automation, 1995

1994

RC interconnect synthesis-a moment fitting approach.

Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis.

Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

A Gate-Delay Model for high-Speed CMOS Circuits.

Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage

Proceedings of the 31st Conference on Design Automation, 1994

1993

Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization.

Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage

Proceedings of the 30th Design Automation Conference. Dallas, 1993