Nobuyoshi Nomizu

According to our database, Nobuyoshi Nomizu authored at least 7 papers between 1980 and 1991.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1991

Timing Optimization on Mapped Circuits.

Ko Yoshikawa, Hiroshi Ichiryu, Hisato Tanishita, Shigenobu Suzuki, Nobuyoshi Nomizu, Akira Kondoh

Proceedings of the 28th Design Automation Conference, 1991

1990

HAL III: function level hardware logic simulation.

Shigeru Takasaki, Nobuyoshi Nomizu, Yoshihiro Hirabayashi, Hiroshi Ishikura, Masahiro Kurashita, Nobuhiko Koike, Toshiyuki Nakata

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

A Framework Environment for Logic Design Support System.

Kaname Kuroki, Nobuyoshi Nomizu, Shigenobu Suzuki, Kazutoshi Takahashi

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1987

Block-Level Hardware Logic Simulation Machine.

Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Nobuhiko Koike, Kenji Ohmori

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1986

HAL II: a mixed level hardware logic simulation system.

Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Hiroshi Ishikura, Nobuhiko Koike

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1984

Logic Design Verification Using Automated Test Generation.

Tohru Sasaki, Shunichi Kato, Nobuyoshi Nomizu, Hidetoshi Tanaka

Proceedings of the Proceedings International Test Conference 1984, 1984

1980

MIXS: A mixed level simulator for large digital system logic verification.

Tohru Sasaki, Akihiko Yamada, Shunichi Kato, Terufumi Nakazawa, Kyoji Tomita, Nobuyoshi Nomizu

Proceedings of the 17th Design Automation Conference, 1980