Nobutaro Shibata

According to our database, Nobutaro Shibata authored at least 16 papers between 1996 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines.

Nobutaro Shibata, Mitsuo Nakamura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

2017

A SOI Multi-<i>V</i>_DD Dual-Port SRAM Macro for Serial Access Applications.

Nobutaro Shibata, Mayumi Watanabe, Takako Ishihara

IEICE Trans. Electron., 2017

2016

A SOI Cache-Tag Memory with Dual-Rail Wordline Scheme.

Nobutaro Shibata, Takako Ishihara

IEICE Trans. Electron., 2016

A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications.

Nobutaro Shibata, Yoshinori Gotoh, Takako Ishihara

IEICE Trans. Electron., 2016

2015

An STM-16 Frame Termination VLSI With 2.5-Gb/s/Pin Input/Output Buffers: High-Speed and Low-Power Multi-𝕍_DD CMOS/SIMOX Techniques.

Nobutaro Shibata, Yusuke Ohtomo, Mika Nishisaka, Yasuhiro Sato

IEEE Trans. Very Large Scale Integr. Syst., 2015

High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost.

Nobutaro Shibata, Yoshinori Gotoh

IEEE Trans. Very Large Scale Integr. Syst., 2015

2010

A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins - Write/Read Assist Techniques for 1-V Operated Memory Cells.

Nobutaro Shibata, Mayumi Watanabe, Hideomi Okiyama

IEEE J. Solid State Circuits, 2010

2006

A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme.

Nobutaro Shibata, Hiroshi Kiya, Shigehiro Kurita, Hidetaka Okamoto, Masa'aki Tan'no, Takakuni Douseki

IEEE J. Solid State Circuits, 2006

2005

A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation.

Takakuni Douseki, Toshishige Shimamura, Nobutaro Shibata

IEICE Trans. Electron., 2005

2002

A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell.

Nobutaro Shibata, Mayumi Watanabe, Yasuyuki Tanabe

IEEE J. Solid State Circuits, 2002

2001

A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs.

Nobutaro Shibata, Mayumi Watanabe, Yasuhiro Sato, Takako Ishihara, Yukio Komine

IEEE J. Solid State Circuits, 2001

2000

1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs.

Nobutaro Shibata, Hiroki Morimura, Mitsuru Harada

IEEE J. Solid State Circuits, 2000

1999

A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers.

Nobutaro Shibata, Hiroki Morimura, Mayumi Watanabe

IEEE J. Solid State Circuits, 1999

1998

A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM's.

Hiroki Morimura, Nobutaro Shibata

IEEE J. Solid State Circuits, 1998

1996

Two-chip MPEG-2 video encoder.

Toshio Kondo, Kazuhito Suguri, Mitsuo Ikeda, Tetsuya Abe, Hiroaki Matsuda, Tsuneo Okubo, Kenji Ogura, Yutaka Tashiro, Naoki Ono, Toshihiro Minami, Ritsu Kusaba, Takeshi Ikenaga, Nobutaro Shibata, Ryota Kasai, Koji Otsu, Fumiaki Nakagawa, Yasuhiko Sato

IEEE Micro, 1996

A 1-V 1-Mb SRAM for portable equipment.

Hiroki Morimura, Nobutaro Shibata

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996