Nobuki Kajihara

According to our database1, Nobuki Kajihara authored at least 15 papers between 1988 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2024
FPGA Implementation for Large Scale Reservoir Computing based on Chaotic Boltzmann Machine.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2001
Implementation of a Gate-Level Evolvable Hardware Chip.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2001

Arithmetic Operation Oriented Reconfigurable Chip: RHW.
Proceedings of the Field-Programmable Logic and Applications, 2001

2000
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
Real-world applications of analog and digital evolvable hardware .
IEEE Trans. Evol. Comput., 1999

The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing.
IEEE Trans. Computers, 1999

Evolvable Hardware Chips for Industrial Applications.
Commun. ACM, 1999

Evolvable Hardware Chips for Neural Network Applications.
Proceedings of the International Conference on Artificial Neural Nets and Genetic Algorithms, 1999

An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand Controller.
Proceedings of the Sixteenth National Conference on Artificial Intelligence and Eleventh Conference on Innovative Applications of Artificial Intelligence, 1999

1998
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI.
Proceedings of the Evolvable Systems: From Biology to Hardware, 1998

Evolvable Hardware Chip for High Precision Printer Image Compression.
Proceedings of the Fifteenth National Conference on Artificial Intelligence and Tenth Innovative Applications of Artificial Intelligence Conference, 1998

1996
SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method.
Proceedings of the Parcella 1996, 1996

SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method.
Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

1989
MAN-YO: Mixed level parallel logic simulation engine.
Syst. Comput. Jpn., 1989

1988
Parallel neural network simulation machine: Neuman.
Neural Networks, 1988


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