Nobuki Kajihara

According to our database, Nobuki Kajihara authored at least 15 papers between 1988 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

FPGA Implementation for Large Scale Reservoir Computing based on Chaotic Boltzmann Machine.

Shigeki Matsumoto, Yuki Ichikawa, Nobuki Kajihara, Hakaru Tamukoh

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2001

Implementation of a Gate-Level Evolvable Hardware Chip.

Masaya Iwata, Isamu Kajitani, Yong Liu, Nobuki Kajihara, Tetsuya Higuchi

Proceedings of the Evolvable Systems: From Biology to Hardware, 2001

Arithmetic Operation Oriented Reconfigurable Chip: RHW.

Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara

Proceedings of the Field-Programmable Logic and Applications, 2001

2000

Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW.

Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara

Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999

Real-world applications of analog and digital evolvable hardware .

Tetsuya Higuchi, Masaya Iwata, Didier Keymeulen, Hidenori Sakanashi, Masahiro Murakawa, Isamu Kajitani, Eiichi Takahashi, Kenji Toda, Mehrdad Salami, Nobuki Kajihara, Nobuyuki Otsu

IEEE Trans. Evol. Comput., 1999

The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing.

Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi

IEEE Trans. Computers, 1999

Evolvable Hardware Chips for Industrial Applications.

Tetsuya Higuchi, Nobuki Kajihara

Commun. ACM, 1999

Evolvable Hardware Chips for Neural Network Applications.

Isamu Kajitani, Masahiro Murakawa, Nobuki Kajihara, Masaya Iwata, Hidenori Sakanashi, Tetsuya Higuchi

Proceedings of the International Conference on Artificial Neural Nets and Genetic Algorithms, 1999

An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand Controller.

Isamu Kajitani, Tsutomu Hoshino, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi

Proceedings of the Sixteenth National Conference on Artificial Intelligence and Eleventh Conference on Innovative Applications of Artificial Intelligence, 1999

1998

A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI.

Isamu Kajitani, Tsutomu Hoshino, Daisuke Nishikawa, Hiroshi Yokoi, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Masaya Iwata, Didier Keymeulen, Tetsuya Higuchi

Proceedings of the Evolvable Systems: From Biology to Hardware, 1998

Evolvable Hardware Chip for High Precision Printer Image Compression.

Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Tetsuya Higuchi

Proceedings of the Fifteenth National Conference on Artificial Intelligence and Tenth Innovative Applications of Artificial Intelligence Conference, 1998

1996

SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method.

Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara

Proceedings of the Parcella 1996, 1996

SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method.

Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara

Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

1989

MAN-YO: Mixed level parallel logic simulation engine.

Nobuhiko Koike, Toshiyuki Nakata, Nobuki Kajihara

Syst. Comput. Jpn., 1989

1988

Parallel neural network simulation machine: Neuman.

Nobuki Kajihara, Satoshi Matsushita, Toshiyuki Nakata, Nobuhiko Koike

Neural Networks, 1988