Nobuhiro Sato

According to our database, Nobuhiro Sato authored at least 4 papers between 2003 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2020

A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications.

Yutaka Yamada, Masato Uchiyama, Masashi Jobashi, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Yoshinari Ojima, Ryusuke Murakami, Takashi Yoshikawa, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda

IEEE J. Solid State Circuits, 2020

2019

A 20.5TOPS and 217.3GOPS/mm² Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications.

Yutaka Yamada, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda, Masato Uchiyama, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Ryusuke Murakami, Takashi Yoshikawa

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2015

18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications.

Jun Tanabe, Toru Sano, Yutaka Yamada, Tomoki Watanabe, Mayu Okumura, Manabu Nishiyama, Tadakazu Nomura, Kazushige Oma, Nobuhiro Sato, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2003

A High Precision IDDQ Measurement System With Improved Dynamic Load Regulation.

Nobuhiro Sato, Yoshihiro Hashimoto

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003