Nobuhiro Ide

According to our database1, Nobuhiro Ide authored at least 6 papers between 1995 and 2000.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2000
Vector Unit Architecture for Emotion Synthesis.
IEEE Micro, 2000

2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing.
IEEE J. Solid State Circuits, 2000


1999
A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder.
IEEE J. Solid State Circuits, 1999

1997
A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1995
30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed Circuit.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995


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