Nobuhiro Ide

According to our database, Nobuhiro Ide authored at least 7 papers between 1993 and 2000.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2000

Vector Unit Architecture for Emotion Synthesis.

Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki

IEEE Micro, 2000

2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing.

Nobuhiro Ide, Masashi Hirano, Yukio Endo, Shin-ichi Yoshioka, Hiroaki Murakami, Atsushi Kunimatsu, Toshinori Sato, Takayuki Kamei, Toyoshi Okada, Masakazu Suzuoki

IEEE J. Solid State Circuits, 2000

300MHz design methodology of VU for emotion synthesis.

Takayuki Kamei, Hideaki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin'ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu

Proceedings of ASP-DAC 2000, 2000

1999

A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder.

Masakazu Suzuoki, Ken Kutaragi, Toshiyuki Hiroi, Hidetaka Magoshi, Shin'ichi Okamoto, Masaaki Oka, Akio Ohba, Yasuyuki Yamamoto, Makoto Furuhashi, Masayoshi Tanaka, Teiji Yutaka, Toyoshi Okada, Masato Nagamatsu, Yukihiro Urakawa, Masami Funyu, Atsushi Kunimatsu, Harutaka Goto, Kazuhiro Hashimoto, Nobuhiro Ide, Hiroaki Murakami, Yukio Ohtaguro, Akira Aono

IEEE J. Solid State Circuits, 1999

1997

A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit.

Gensoh Matsubara, Nobuhiro Ide

Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1995

30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed Circuit.

Gensoh Matsubara, Nobuhiro Ide, Haruyuki Tago, Seigo Suzuki, Nobuyuki Goto

Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1993

A 320 MFLOPS CMOS floating-point processing unit for superscalar processors.

Nobuhiro Ide, Hiroto Fukuhisa, Yoshihisa Kondo, Takeshi Yoshida, Masato Nagamatsu, Junji Mori, Itaru Yamazaki, Kiyoyi Ueno

IEEE J. Solid State Circuits, March, 1993