Nobuaki Okada

According to our database, Nobuaki Okada authored at least 7 papers between 2007 and 2012.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2012

A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme.

Xu Bai, Nobuaki Okada, Michitaka Kameyama

J. Multiple Valued Log. Soft Comput., 2012

2010

Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits.

Nobuaki Okada, Michitaka Kameyama

IEICE Trans. Inf. Syst., 2010

Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals.

Akitaka Ishikawa, Nobuaki Okada, Michitaka Kameyama

Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

2009

Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals.

Nobuaki Okada, Michitaka Kameyama

Proceedings of the ISMVL 2009, 2009

2008

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation.

Nobuaki Okada, Michitaka Kameyama

IEICE Trans. Electron., 2008

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells.

Nobuaki Okada, Michitaka Kameyama

Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

2007

Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits.

Nobuaki Okada, Michitaka Kameyama

J. Multiple Valued Log. Soft Comput., 2007