Noboru Tanabe

According to our database, Noboru Tanabe authored at least 29 papers between 1989 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2018

Characterizing Memory-Latency Sensitivity of Sparse Matrix Kernels.

Noboru Tanabe, Toshio Endo

Proceedings of the 26th Euromicro International Conference on Parallel, 2018

Exhaustive evaluation of memory-latency sensitivity on manycore processors with large cache.

Noboru Tanabe, Toshio Endo

Proceedings of the 2nd International Conference on High Performance Compilation, 2018

2013

Network Interface Architecture with Scalable Low-Latency Message Receiving Mechanism.

Noboru Tanabe, Atsushi Ohta

IEICE Trans. Inf. Syst., 2013

Character of Graph Analysis Workloads and Recommended Solutions on Future Parallel Systems.

Noboru Tanabe, Sonoko Tomimori, Masami Takata, Kazuki Joe

Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

2011

A memory accelerator with gather functions for bandwidth-bound irregular applications.

Noboru Tanabe, Boonyasitpichai Nuttapon, Hironori Nakajo, Yuka Ogawa, Junko Kogou, Masami Takata, Kazuki Joe

Proceedings of the first workshop on Irregular applications: architectures and algorithm, 2011

Scaleable Sparse Matrix-Vector Multiplication with Functional Memory and GPUs.

Noboru Tanabe, Yuuka Ogawa, Masami Takata, Kazuki Joe

Proceedings of the 19th International Euromicro Conference on Parallel, 2011

2010

An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing.

Noboru Tanabe, Hirotaka Hakozaki, Hiroshi Ando, Yasunori Dohi, Zhengzhe Luo, Hironori Nakajo

J. Supercomput., 2010

Acceleration for MPI derived datatypes using an enhancer of memory and network.

Noboru Tanabe, Hironori Nakajo

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

2009

The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing.

Noboru Tanabe, Manami Sasaki, Hironori Nakajo, Masami Takata, Kazuki Joe

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

Network Interface Architecture for Scalable Message Queue Processing.

Noboru Tanabe, Atsushi Ohta, Pulung Waskito, Hironori Nakajo

Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

2008

Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network.

Noboru Tanabe, Hironori Nakajo

Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 2008

An Enhancer of Memory and Network for Cluster and its Applications.

Noboru Tanabe, Hironori Nakajo

Proceedings of the Ninth International Conference on Parallel and Distributed Computing, 2008

2007

Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs.

Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano

IEEE Trans. Parallel Distributed Syst., 2007

Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot.

Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007

Performance evaluation on low-latency communication mechanism of DIMMnet-2.

Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano

Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2007

2006

Implementation of PC Cluster System with Memory Mapped File by Commodity OS.

Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot.

Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005

A Packet Forwarding Layer for DIMMnet and its Hardware Implementation.

Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board.

Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo

Proceedings of the Sixth International Conference on Parallel and Distributed Computing, 2005

Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2.

Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyashiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano

Proceedings of the High-Performance Computing - 6th International Symposium, 2005

2004

A New Memory Module for Memory Intensive Applications.

Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

2002

Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot.

Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano

Clust. Comput., 2002

Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot.

Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano

Proceedings of the 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 2002

2000

On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism.

Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano

Proceedings of the 5th International Symposium on Parallel Architectures, 2000

MEMOnet : Network interface plugged into a memory slot.

Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano

Proceedings of the 2000 IEEE International Conference on Cluster Computing (CLUSTER 2000), November 28th, 2000

1996

Improving the performance of global communication on a three-dimensional torus network.

Yasushi Kawakura, Noboru Tanabe, Shigeru Oyanagi

Syst. Comput. Jpn., 1996

1992

Implementation of the prodigy parallel AI machine and performance evaluation of communication.

Noboru Tanabe, Sadao Nakamura, Takashi Suzuoka, Shigeru Oyanagi

Syst. Comput. Jpn., 1992

1991

Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGY.

Noboru Tanabe, Takashi Suzuoka, Sadao Nakamura, Yasushi Kawakura, Shigeru Oyanagi

Proceedings of the International Conference on Parallel Processing, 1991

1989

Network Performance of the Prodigy Parallel AI Machine.

Takashi Suzuoka, Noboru Tanabe, Sadao Nakamura, Sumikazu Fujita, Shigeru Oyanagi

Syst. Comput. Jpn., 1989