Noboru Shibata

Orcid: 0000-0002-1988-2520

According to our database1, Noboru Shibata authored at least 15 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2024
Fast Readable Multi-Cell Coding for Flash Memory.
Proceedings of the IEEE International Symposium on Information Theory, 2024

Novel Multi-Level Coding and Architecture Enabling Fast Random Access for Flash Memory.
Proceedings of the IEEE International Memory Workshop, 2024

2023
A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface.
IEEE J. Solid State Circuits, 2023

7-Bit/2Cell (X3.5), 9-Bit/2Cell (X4.5) NAND Flash Memory: Half Bit technology.
Proceedings of the IEEE International Memory Workshop, 2023

2022

2020
A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology.
IEEE J. Solid State Circuits, 2020

2019


2018

2013
A 19 nm 112.8 mm<sup>2</sup> 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface.
IEEE J. Solid State Circuits, 2013

2012
An Embedded DRAM Technology for High-Performance NAND Flash Memories.
IEEE J. Solid State Circuits, 2012


2009

2008
A 70 nm 16 Gb 16-Level-Cell NAND flash Memory.
IEEE J. Solid State Circuits, 2008

2006
A 146-mm<sup>2</sup> 8-gb multi-level NAND flash memory with 70-nm CMOS technology.
IEEE J. Solid State Circuits, 2006


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