Noboru Shibata
Orcid: 0000-0002-1988-2520
According to our database1,
Noboru Shibata
authored at least 15 papers
between 2006 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the IEEE International Symposium on Information Theory, 2024
Novel Multi-Level Coding and Architecture Enabling Fast Random Access for Flash Memory.
Proceedings of the IEEE International Memory Workshop, 2024
2023
IEEE J. Solid State Circuits, 2023
Proceedings of the IEEE International Memory Workshop, 2023
2022
A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2020
IEEE J. Solid State Circuits, 2020
2019
A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2013
A 19 nm 112.8 mm<sup>2</sup> 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface.
IEEE J. Solid State Circuits, 2013
2012
IEEE J. Solid State Circuits, 2012
A 19nm 112.8mm<sup>2</sup> 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
2006
IEEE J. Solid State Circuits, 2006