Noboru Sakimura

According to our database1, Noboru Sakimura authored at least 20 papers between 2007 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2016
Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory.
J. Multiple Valued Log. Soft Comput., 2016

2015
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.
IEEE J. Solid State Circuits, 2015

2014
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure.
IEICE Electron. Express, 2014

Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme.
IEICE Electron. Express, 2014

A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Soft-Delay-Error Evaluation in Content-Addressable Memory.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes.
IPSJ Trans. Syst. LSI Des. Methodol., 2013

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
High-speed simulator including accurate MTJ models for spintronics integrated circuit design.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009
Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs.
IEEE J. Solid State Circuits, 2009

Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros.
IEICE Trans. Electron., 2009


2007
A 16-Mb Toggle MRAM With Burst Modes.
IEEE J. Solid State Circuits, 2007

MRAM Cell Technology for Over 500-MHz SoC.
IEEE J. Solid State Circuits, 2007

MRAM Applications Using Unlimited Write Endurance.
IEICE Trans. Electron., 2007

Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode.
IEICE Trans. Electron., 2007


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