Noboru Masuda

According to our database, Noboru Masuda authored at least 10 papers between 1990 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion.

Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura

IEEE J. Solid State Circuits, 2014

2012

A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS.

Takashi Takemoto, Hiroki Yamashita, Takehito Kamimura, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Kenji Kogo, Yong Lee, Shinji Tsuji, Shinji Nishimura

Proceedings of the Symposium on VLSI Circuits, 2012

2011

A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link.

Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura

IEEE J. Solid State Circuits, 2011

10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link.

Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process.

Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Noboru Masuda, Takashi Takemoto, Fumio Yuki, Tatsuya Saito

IEEE J. Solid State Circuits, 2010

2003

A Study of a Stable Driving Circuit for Arbitrary-Shaped Electroluminescent Elements.

Yasuyuki Kitada, Noboru Masuda, Hiroshi Nakane, Sadao Yamazaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

1994

Impedance Measurement and Analysis of Water-Containing Foodstuffs in Refrigeration Process.

Hideo Kusano, Teruo Negishi, Noboru Masuda

J. Robotics Mechatronics, 1994

1993

A self-learning digital neural network using wafer-scale LSI.

Moritoshi Yasunaga, Noboru Masuda, Masayoshi Yagyu, Mitsuo Asai, Katsunari Shibata, Mitsuo Ooyama, Minoru Yamada, Takahiro Sakaguchi, Masashi Hashimoto

IEEE J. Solid State Circuits, February, 1993

A Novel Clock Distribution System for CMOS VLSI.

Kenichi Ishibashi, Takehisa Hayashi, Toshio Doi, Noboru Masuda, Akira Yamagiwa, Toshihiro Okabe

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1990

Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons.

Moritoshi Yasunaga, Noboru Masuda, Masayoshi Yagyu, Mitsuo Asai, Minoru Yamada, Akira Masaki

Proceedings of the IJCNN 1990, 1990