Nizar Dahir

Orcid: 0000-0003-3466-0982

According to our database¹, Nizar Dahir authored at least 18 papers between 2011 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2022

Thermal and Performance Efficient On-Chip Surface-Wave Communication for Many-Core Systems in Dark Silicon Era.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

2021

Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach.

[BibT_eX]

[DOI]

Integr., 2021

2018

Network-on-Chip Multicast Architectures Using Hybrid Wire and Surface-Wave Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2018

2017

LeAF: A low-overhead asymmetric frequency controller for NoC router interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Optimized task graph mapping on a many-core neuromorphic supercomputer.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

2016

Fault tolerant task mapping on many-core arrays.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016

XL-STaGe: A cross-layer scalable tool for graph generation, evaluation and implementation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

MEMS-based power delivery control for bursty applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Characterisation of feasibility regions in FPGAs under adaptive DVFS.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014

Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2013

2012

Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

Minimizing power supply noise through harmonic mappings in networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

Communication centric on-chip power grid models for networks-on-chip.

[BibT_eX]

[DOI]

Nizar Dahir

Terrence S. T. Mak

Alex Yakovlev

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Nizar Dahir

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