Nivedita Shrivastava

Orcid: 0000-0001-8378-3634

According to our database1, Nivedita Shrivastava authored at least 10 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
SecScale: A Scalable and Secure Trusted Execution Environment for Servers.
CoRR, 2024

NeuroPlug: Plugging Side-Channel Leaks in NPUs using Space Filling Curves.
CoRR, 2024

2023
Toward an Optimal Countermeasure for Cache Side-Channel Attacks.
IEEE Embed. Syst. Lett., September, 2023

SparseLock: Securing Neural Network Models in Deep Learning Accelerators.
CoRR, 2023

SecOComp: A Fast and Secure Simultaneous Compression and Encryption Scheme.
CoRR, 2023

Securator: A Fast and Secure Neural Processing Unit.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022
Seculator: A Fast and Secure Neural Processing Unit.
CoRR, 2022

PredStereo: An Accurate Real-time Stereo Vision System.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2022

2021
A survey of hardware architectures for generative adversarial networks.
J. Syst. Archit., 2021

2020
Efficient hardware implementations of QTL cipher for RFID applications.
Int. J. High Perform. Syst. Archit., 2020


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