Nitin Chawla

According to our database, Nitin Chawla authored at least 11 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Roadmap to Neuromorphic Computing with Emerging Technologies.

Adnan Mehonic, Daniele Ielmini, Kaushik Roy, Onur Mutlu, Shahar Kvatinsky, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Sabina Spiga, Sergey Savelev, Alexander G. Balanov, Nitin Chawla, Giuseppe Desoli, Gerardo Malavena, Christian Monzio Compagnoni, Zhongrui Wang, J. Joshua Yang, Syed Ghazi Sarwat, Abu Sebastian, Thomas Mikolajick, Beatriz Noheda, Stefan Slesazeck, Bernard Dieny, Tuo-Hung Hou, Akhil Varri, Frank Brückerhoff-Plückelmann, Wolfram H. P. Pernice, Xixiang Zhang, Sebastian Pazos, Mario Lanza, Stefan Wiefels, Regina Dittmann, Wing H. Ng, Mark Buckwell, Horatio Cox, Daniel J. Mannion, Anthony J. Kenyon, Yingming Lu, Yuchao Yang, Damien Querlioz, Louis Hutin, Elisa Vianello, Sayeed Shafayet Chowdhury, Piergiulio Mannocci, Yimao Cai, Zhong Sun, Giacomo Pedretti, John Paul Strachan, Dmitri B. Strukov, Manuel Le Gallo, Stefano Ambrogio, Ilia Valov, Rainer Waser

CoRR, 2024

2023

A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications.

Giuseppe Desoli, Nitin Chawla, Thomas Boesch, Manui Avodhyawasi, Harsh Rawat, Hitesh Chawla, VS Abhijith, Paolo Zambotti, Akhilesh Sharma, Carmine Cappetta, Michele Rossi, Antonio De Vita, Francesca Girardi

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021

Artificial Intelligence: Why moving it to the Edge?

Joël Hartmann, Paolo Cappelletti, Nitin Chawla, Franck Arnaud, Andreia Cathelin

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2020

Improving Cost for Data Migration in Cloud Computing Using Genetic Algorithm.

Nitin Chawla, Deepak Kumar, Dinesh Kumar Sharma

Int. J. Softw. Innov., 2020

2018

Modelling of Cloud Computing Enablers Using MICMAC Analysis and TISM.

Nitin Chawla, Deepak Kumar

Int. J. Ambient Comput. Intell., 2018

2017

14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems.

Giuseppe Desoli, Nitin Chawla, Thomas Boesch, Surinder Pal Singh, Elio Guidetti, Fabio De Ambroggi, Tommaso Majo, Paolo Zambotti, Manuj Ayodhyawasi, Harvinder Singh, Nalin Aggarwal

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

The Orlando Project: A 28 nm FD-SOI Low Memory Embedded Neural Network ASIC.

Giuseppe Desoli, Valeria Tomaselli, Emanuele Plebani, Giulio Urlini, Danilo Pau, Viviana D'Alto, Tommaso Majo, Fabio De Ambroggi, Thomas Boesch, Surinder Pal Singh, Elio Guidetti, Nitin Chawla

Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2016

2010

A 1 GHz Digital Channel Multiplexer for Satellite Outdoor Unit.

Pierre Busson, Nitin Chawla, Jérôme Bach, Stéphane Le Tual, Harvinder Singh, Vineet Gupta, Pascal Urard

IEEE J. Solid State Circuits, 2010

2009

A 1GHz digital channel multiplexer for satellite OutDoor Unit based on a 65nm CMOS transceiver.

Pierre Busson, Nitin Chawla, Jérôme Bach, Stéphane Le Tual, Harvinder Singh, Vineet Gupta, Pascal Urard

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling Satellite-Transmission Portable Devices.

Pascal Urard, L. Paumier, V. Heinrich, N. Raina, Nitin Chawla

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Leveraging sequential equivalence checking to enable system-level to RTL flows.

Pascal Urard, Asma Maalej, Roberto Guizzetti, Nitin Chawla

Proceedings of the 45th Design Automation Conference, 2008