Nitin Chaturvedi

According to our database, Nitin Chaturvedi authored at least 12 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher.

Kartik Jhawar, Jugal Gandhi, Diksha Shekhawat, Aniket Upadhyay, Avadh Harkishanka, Nitin Chaturvedi, M. Santosh, Jai Gopal Pandey

J. Real Time Image Process., April, 2024

2022

Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity Against Process Variations.

Kanika Monga, Eesha Karnawat, Nitin Chaturvedi, S. Gurunarayanan

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021

Design of an MTJ/CMOS-Based Asynchronous System for Ultra-Low Power Energy Autonomous Applications.

Kanika Monga, Kunal Harbhajanka, Arush Srivastava, Nitin Chaturvedi, S. Gurunarayanan

J. Circuits Syst. Comput., 2021

Drone-MAP: A Novel Authentication Scheme for Drone-Assisted 5G Networks.

Tejasvi Alladi, Vishnu Venkatesh, Vinay Chamola, Nitin Chaturvedi

Proceedings of the 2021 IEEE Conference on Computer Communications Workshops, 2021

2020

Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array.

Kanika Monga, Lakshaya Maheshwari, Nitin Chaturvedi, S. Gurunarayanan

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019

A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications.

Kanika, R. Sankara Prasad, Nitin Chaturvedi, S. Gurunarayanan

Integr., 2019

A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications.

Kanika Monga, Nitin Chaturvedi

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

A Novel Low Power Non-Volatile SRAM Cell with Self Write Termination.

Kanika Monga, Akul Malhotra, Nitin Chaturvedi, S. Gurunayaranan

Proceedings of the 10th International Conference on Computing, 2019

2018

An FPGA Based Hardware Accelerator for Classification of Handwritten Digits.

R. Gautham Sundar Ram, Nitin Chaturvedi, Sumeet Saurav, Sanjay Singh

Proceedings of the Intelligent Systems Design and Applications, 2018

2016

An Investigation of Power-Performance Aware Accelerator/Core Allocation Challenges in Dark Silicon Heterogeneous Systems.

Pranshu Kalra, Shaista Hussain, Nitin Chaturvedi

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

2015

An adaptive migration-replication scheme (AMR) for shared cache in chip multiprocessors.

Nitin Chaturvedi, Arun Subramaniyan, S. Gurunarayanan

J. Supercomput., 2015

An efficient adaptive block pinning for multicore architectures.

Nitin Chaturvedi, S. Gurunarayanan

Microprocess. Microsystems, 2015