Nitin Chandrachoodan

According to our database, Nitin Chandrachoodan authored at least 56 papers between 1999 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

AlphaZip: Neural Network-Enhanced Lossless Text Compression.

Swathi Shree Narashiman, Nitin Chandrachoodan

CoRR, 2024

2023

Snoopy: A Webpage Fingerprinting Framework With Finite Query Model for Mass-Surveillance.

Gargi Mitra, Prasanna Karthik Vairam, Sandip Saha, Nitin Chandrachoodan, V. Kamakoti

IEEE Trans. Dependable Secur. Comput., 2023

Slimmer CNNs Through Feature Approximation and Kernel Size Reduction.

Dara Nagaraju, Nitin Chandrachoodan

IEEE Open J. Circuits Syst., 2023

Compressing fully connected layers of deep neural networks using permuted features.

Dara Nagaraju, Nitin Chandrachoodan

IET Comput. Digit. Tech., 2023

ViTA: A Vision Transformer Inference Accelerator for Edge Applications.

Shashank Nag, Gourav Datta, Souvik Kundu, Nitin Chandrachoodan, Peter A. Beerel

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Work-in-Progress: QRCNN: Scalable CNNs.

Dara Nagaraju, Nitin Chandrachoodan

Proceedings of the International Conference on Compilers, 2023

2022

Reduced Memory Viterbi Decoding for Hardware-accelerated Speech Recognition.

Pani Prithvi Raj, Akhil Reddy Pakala, Nitin Chandrachoodan

ACM Trans. Embed. Comput. Syst., 2022

Layerwise Disaggregated Evaluation of Spiking Neural Networks.

Abinand Nallathambi, Sanchari Sen, Anand Raghunathan, Nitin Chandrachoodan

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

Split-Knit Convolution: Enabling Dense Evaluation of Transpose and Dilated Convolutions on GPUs.

Arjun Menon Vadakkeveedu, Debabrata Mandal, Pradeep Ramachandran, Nitin Chandrachoodan

Proceedings of the 29th IEEE International Conference on High Performance Computing, 2022

2021

Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders.

Celia Dharmaraj, Vinita Vasudevan, Nitin Chandrachoodan

ACM Trans. Embed. Comput. Syst., 2021

A Smoothed LASSO-Based DNN Sparsification Technique.

Basava Naga Girish Koneru, Nitin Chandrachoodan, Vinita Vasudevan

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Analysis of power-accuracy trade-off in digital signal processing applications using low-power approximate adders.

Celia Dharmaraj, Vinita Vasudevan, Nitin Chandrachoodan

IET Comput. Digit. Tech., 2021

2020

Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips.

Gokulkrishnan Vadakkeveedu, Kamakoti Veezhinathan, Nitin Chandrachoodan, Seetal Potluri

IET Comput. Digit. Tech., 2020

Probabilistic spike propagation for FPGA implementation of spiking neural networks.

Abinand Nallathambi, Nitin Chandrachoodan

CoRR, 2020

Energy Reduction in Turbo Decoding through Dynamically Varying Bit-Widths.

Sundarrajan Rangachari, Nitin Chandrachoodan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

EASpiNN: Effective Automated Spiking Neural Network Evaluation on FPGA.

Sathish Panchapakesan, Zhenman Fang, Nitin Chandrachoodan

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Depending on HTTP/2 for Privacy? Good Luck!

Gargi Mitra, Prasanna Karthik Vairam, Patanjali SLPSK, Nitin Chandrachoodan, Kamakoti Veezhinathan

Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2020

2019

A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits.

Shivani Bathla, Rahul M. Rao, Nitin Chandrachoodan

IEEE Trans. Very Large Scale Integr. Syst., 2019

White Mirror: Leaking Sensitive Information from Interactive Netflix Movies using Encrypted Traffic Analysis.

Gargi Mitra, Prasanna Karthik Vairam, Patanjali SLPSK, Nitin Chandrachoodan, Kamakoti Veezhinathan

Proceedings of the ACM SIGCOMM 2019 Conference Posters and Demos, 2019

Data Subsetting: A Data-Centric Approach to Approximate Computing.

Younghoon Kim, Swagath Venkataramani, Nitin Chandrachoodan, Anand Raghunathan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Probabilistic Error Modeling for Two-part Segmented Approximate Adders.

D. Celia, Vinita Vasudevan, Nitin Chandrachoodan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Lossless Parallel Implementation of a Turbo Decoder on GPU.

Karthikeyan Natarajan, Nitin Chandrachoodan

Proceedings of the 25th IEEE International Conference on High Performance Computing, 2018

Optimizing power-accuracy trade-off in approximate adders.

D. Celia, Vinita Vasudevan, Nitin Chandrachoodan

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Scenario-Aware Dynamic Power Reduction Using Bias Addition.

Sundarrajan Rangachari, Jaiganesh Balakrishnan, Nitin Chandrachoodan

IEEE Trans. Very Large Scale Integr. Syst., 2017

FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only).

Srinivas Siripurapu, Aman Gayasen, Padmini Gopalakrishnan, Nitin Chandrachoodan

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips.

Gokulkrishnan Vadakkeveedu, V. Kamakoti, Nitin Chandrachoodan, Seetal Potluri

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016

FFT/IFFT implementation using Vivado™ HLS.

Amit Salaskar, Nitin Chandrachoodan

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Guided multilevel approximation of less significant bits for power reduction.

D. Celia, Nitin Chandrachoodan

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015

DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing.

Seetal Potluri, Satya Trinadh, Ch. Sobhan Babu, V. Kamakoti, Nitin Chandrachoodan

ACM Trans. Design Autom. Electr. Syst., 2015

Designing a passive star optical network for the India-based Neutrino Observatory.

Vaibhav Pratap Singh, Nitin Chandrachoodan, Anil Prabhakar

Proceedings of the Twenty First National Conference on Communications, 2015

Non-uniform DFT implementation for channel simulations in GPU.

Karthikeyan Natarajan, Nitin Chandrachoodan

Proceedings of the Twenty First National Conference on Communications, 2015

iitRACE: A Memory Efficient Engine for Fast Incremental Timing Analysis and Clock Pessimism Removal.

Chaitanya Peddawad, Aman Goel, B. Dheeraj, Nitin Chandrachoodan

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

Scalable Low Power FFT/IFFT Architecture with Dynamic Bit Width Configurability.

Sundarrajan Rangachari, Jaiganesh Balakrishnan, Nitin Chandrachoodan

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013

Tutorial T1B: Riding the "Energy Consumption Horse" - from System-level Design to Silicon.

Prabhat Avasare, Nitin Chandrachoodan

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Scalable low power digital filter architectures for varying input dynamic range.

Sundarrajan Rangachari, Nitin Chandrachoodan

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information.

Seetal Potluri, Satya Trinadh, Roopashree Baskaran, Nitin Chandrachoodan, V. Kamakoti

Proceedings of the 18th IEEE European Test Symposium, 2013

An inertial sensor-based system to develop motor capacity in children with cerebral palsy.

Shuo Qiao, Anil Prabhakar, Nitin Chandrachoodan, Namita Jacob, Harshvardhan Vathsangam

Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization.

Vimitha A. Kuruvilla, Debjit Sinha, Jeff Piaget, Chandu Visweswariah, Nitin Chandrachoodan

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture.

Manish Kumar Jaiswal, Nitin Chandrachoodan

IEEE Trans. Computers, 2012

Interconnect Aware Test Power Reduction.

Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti

J. Low Power Electron., 2012

GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications.

Dhiraj Reddy Nallapa Yoge, Nitin Chandrachoodan

Proceedings of the 25th International Conference on VLSI Design, 2012

A GPU implementation of belief propagation decoder for polar codes.

Bharath Kumar Reddy L., Nitin Chandrachoodan

Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011

24th "IEEE International Conference on VLSI Design" Chennai, India, 2-7 January 2011.

Nitin Chandrachoodan, Shankar Balachandran

J. Low Power Electron., 2011

Post-Synthesis Circuit Techniques for Runtime Leakage Reduction.

Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2009

Efficient Implementation of Floating-Point Reciprocator on FPGA.

Manish Kumar Jaiswal, Nitin Chandrachoodan

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008

Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models.

Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA.

Manish Kumar Jaiswal, Nitin Chandrachoodan

Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

2007

Rapid Abstract Control Model for Signal Processing Implementation.

Kannan Gaddam, Nitin Chandrachoodan, S. Srinivasan

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation.

Karthick Parashar, Nitin Chandrachoodan

Proceedings of the FPL 2007, 2007

2004

The hierarchical timing pair model for multirate DSP applications.

Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu

IEEE Trans. Signal Process., 2004

2003

Algorithm and VLSI architecture for high performance adaptive video scaling.

Arun Raghupathy, Nitin Chandrachoodan, K. J. Ray Liu

IEEE Trans. Multim., 2003

2002

High-Level Synthesis of DSP Applications Using Adaptive Negative Cycle Detection.

Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu

EURASIP J. Adv. Signal Process., 2002

2001

The hierarchical timing pair model.

Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Adaptive negative cycle detection in dynamic graphs.

Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

An efficient timing model for hardware implementation of multirate dataflow graphs.

Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu

Proceedings of the IEEE International Conference on Acoustics, 2001

1999

VLSI architecture and design for high performance adaptive video scaling.

Arun Raghupathy, Pohsiang Hsu, K. J. Ray Liu, Nitin Chandrachoodan

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999