Nithyashankari Gummidipoondi Jayasankaran

According to our database, Nithyashankari Gummidipoondi Jayasankaran authored at least 7 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES.

Nithyashankari Gummidipoondi Jayasankaran, Hao Guo, Satwik Patnaik, Jeyavijayan Rajendran, Jiang Hu

CoRR, 2023

2022

Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction.

Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran

IEEE Trans. Emerg. Top. Comput., 2022

2021

Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges.

Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, Jiang Hu, Jeyavijayan Rajendran, Edgar Sánchez-Sinencio

IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020

Breaking Analog Locking Techniques.

Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran

IEEE Trans. Very Large Scale Integr. Syst., 2020

Keynote: A Disquisition on Logic Locking.

Abhishek Chakraborty, Nithyashankari Gummidipoondi Jayasankaran, Yuntao Liu, Jeyavijayan Rajendran, Ozgur Sinanoglu, Ankur Srivastava, Yang Xie, Muhammad Yasin, Michael Zuzak

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits.

Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, S. Y. Lee, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan (JV) Rajendran

Proceedings of the IEEE International Test Conference, 2020

2019

Breaking Analog Locking Techniques via Satisfiability Modulo Theories.

Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran

Proceedings of the IEEE International Test Conference, 2019