Nithin George

According to our database, Nithin George authored at least 13 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

CodePin: An Instrumentation-Based Debug Tool of SYCLomatic.

Andy Huang, Zhiming Wang, Wenhui Ni, Sheng Chen, Nithin George

Proceedings of the 12th International Workshop on OpenCL and SYCL, 2024

2020

SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs.

Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2017

Virtualized Execution Runtime for FPGA Accelerators in the Cloud.

Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne

IEEE Access, 2017

Design Space Exploration of LDPC Decoders Using High-Level Synthesis.

João Andrade, Nithin George, Kimon Karras, David Novo, Frederico Pratas, Leonel Sousa, Paolo Ienne, Gabriel Falcão, Vítor Silva

IEEE Access, 2017

2016

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages.

Nithin George

PhD thesis, 2016

Enriching C-based High-Level Synthesis with parallel pattern templates.

Lana Josipovic, Nithin George, Paolo Ienne

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Designing a virtual runtime for FPGA accelerators in the cloud.

Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

Automatic support for multi-module parallelism from computational patterns.

Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun, Paolo Ienne

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis.

João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders.

João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014

Hardware system synthesis from Domain-Specific Languages.

Nithin George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, Paolo Ienne

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

Making domain-specific hardware synthesis tools cost-efficient.

Nithin George, David Novo, Tiark Rompf, Martin Odersky, Paolo Ienne

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012

Reducing the cost of floating-point mantissa alignment and normalization in FPGAs.

Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012