Nishit Ashok Kapadia
According to our database1,
Nishit Ashok Kapadia
authored at least 13 papers
between 2011 and 2017.
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Bibliography
2017
A Runtime Framework for Robust Application Scheduling With Adaptive Parallelism in the Dark-Silicon Era.
IEEE Trans. Very Large Scale Integr. Syst., 2017
ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-Based Chip Multiprocessors.
IEEE Trans. Multi Scale Comput. Syst., 2017
2016
A System-Level Cosynthesis Framework for Power Delivery and On-Chip Data Networks in Application-Specific 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2016
CHARM: A checkpoint-based resource management framework for reliable multicore computing in the dark silicon era.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
Process variation aware dynamic power management in multicore systems with extended range voltage/frequency scaling.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
VARSHA: variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
PRATHAM: A power delivery-aware and thermal-aware mapping framework for parallel embedded applications on 3D MPSoCs.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
2013
VERVE: A framework for variation-aware energy efficient synthesis of NoC-based MPSoCs with voltage islands.
Proceedings of the International Symposium on Quality Electronic Design, 2013
A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs.
Proceedings of the International Symposium on Quality Electronic Design, 2013
2012
A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands.
Integr., 2012
A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands.
Proceedings of the 25th International Conference on VLSI Design, 2012
2011
VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011