Nishil Talati

According to our database, Nishil Talati authored at least 26 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication.

Kuan-Yu Chen, Thomas Mason Nelson, Alireza Khadem, Morteza Fayazi, Sanjay Sri Vallabh Singapuram, Ronald G. Dreslinski, Nishil Talati, Hun-Seok Kim, David T. Blaauw

ACM Trans. Reconfigurable Technol. Syst., December, 2024

Accurate and Fast Estimation of Temporal Motifs using Path Sampling.

Yunjie Pan, Omkar Bhalerao, C. Seshadhri, Nishil Talati

CoRR, 2024

QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms.

Julian Pavon, Iván Vargas Valdivieso, Carlos Rojas, César Hernández, Mehmet Aslan, Roger Figueras, Yichao Yuan, Joël Lindegger, Mohammed Alser, Francesc Moll, Santiago Marco-Sola, Oguz Ergin, Nishil Talati, Onur Mutlu, Osman S. Unsal, Mateo Valero, Adrián Cristal

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

Understanding the Performance and Estimating the Cost of LLM Fine-Tuning.

Yuchen Xia, Jiho Kim, Yuhan Chen, Haojie Ye, Souvik Kundu, Cong Callie Hao, Nishil Talati

Proceedings of the IEEE International Symposium on Workload Characterization, 2024

2023

Demystifying Graph Sparsification Algorithms in Graph Properties Preservation.

Yuhan Chen, Haojie Ye, Sanketh Vedula, Alex M. Bronstein, Ronald G. Dreslinski, Trevor N. Mudge, Nishil Talati

Proc. VLDB Endow., November, 2023

Everest: GPU-Accelerated System For Mining Temporal Motifs.

Yichao Yuan, Haojie Ye, Sanketh Vedula, Wynn Kaza, Nishil Talati

Proc. VLDB Endow., 2023

Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher.

Yichen Yang, Jingtao Li, Nishil Talati, Subhankar Pal, Siying Feng, Chaitali Chakrabarti, Trevor N. Mudge, Ronald G. Dreslinski

CoRR, 2023

RecPIM: A PIM-Enabled DRAM-RRAM Hybrid Memory System For Recommendation Models.

Heewoo Kim, Haojie Ye, Trevor N. Mudge, Ronald G. Dreslinski, Nishil Talati

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Vector-Processing for Mobile Devices: Benchmark and Analysis.

Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das

Proceedings of the IEEE International Symposium on Workload Characterization, 2023

PEDAL: A Power Efficient GCN Accelerator with Multiple DAtafLows.

Yuhan Chen, Alireza Khadem, Xin He, Nishil Talati, Tanvir Ahmed Khan, Trevor N. Mudge

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

GRACE: A Scalable Graph-Based Approach to Accelerating Recommendation Model Inference.

Haojie Ye, Sanketh Vedula, Yuhan Chen, Yichen Yang, Alex M. Bronstein, Ronald G. Dreslinski, Trevor N. Mudge, Nishil Talati

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

Mint: An Accelerator For Mining Temporal Motifs.

Nishil Talati, Haojie Ye, Sanketh Vedula, Kuan-Yu Chen, Yuhan Chen, Daniel Liu, Yichao Yuan, David T. Blaauw, Alex M. Bronstein, Trevor N. Mudge, Ronald G. Dreslinski

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

NDMiner: accelerating graph pattern mining using near data processing.

Nishil Talati, Haojie Ye, Yichen Yang, Leul Belayneh, Kuan-Yu Chen, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Locality-Aware Optimizations for Improving Remote Memory Latency in Multi-GPU Systems.

Leul Belayneh, Haojie Ye, Kuan-Yu Chen, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski, Nishil Talati

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021

A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors.

Heewoo Kim, Aporva Amarnath, Javad Bagherzadeh, Nishil Talati, Ronald G. Dreslinski

ACM J. Emerg. Technol. Comput. Syst., 2021

A Deep Dive Into Understanding The Random Walk-Based Temporal Graph Learning.

Nishil Talati, Di Jin, Haojie Ye, Ajay Brahmakshatriya, Ganesh S. Dasika, Saman P. Amarasinghe, Trevor N. Mudge, Danai Koutra, Ronald G. Dreslinski

Proceedings of the IEEE International Symposium on Workload Characterization, 2021

Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design.

Nishil Talati, Kyle May, Armand Behroozi, Yichen Yang, Kuba Kaszyk, Christos Vasiladiotis, Tarunesh Verma, Lu Li, Brandon Nguyen, Jiawen Sun, John Magnus Morton, Agreen Ahmadi, Todd M. Austin, Michael F. P. O'Boyle, Scott A. Mahlke, Trevor N. Mudge, Ronald G. Dreslinski

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020

CoPTA: Contiguous Pattern Speculating TLB Architecture.

Yichen Yang, Haojie Ye, Yuhan Chen, Xueyang Liu, Nishil Talati, Xin He, Trevor N. Mudge, Ronald G. Dreslinski

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

2019

CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM.

Nishil Talati, Heonjae Ha, Ben Perach, Ronny Ronen, Shahar Kvatinsky

IEEE Micro, 2019

A Taxonomy and Evaluation Framework for Memristive Logic.

John Reuben, Nishil Talati, Nimrod Wald, Rotem Ben Hur, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky

Proceedings of the Handbook of Memristor Networks., 2019

2018

Practical challenges in delivering the promises of real processing-in-memory machines.

Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Memristive logic: A framework for evaluation and comparison.

John Reuben, Rotem Ben Hur, Nimrod Wald, Nishil Talati, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Rate-compatible and high-throughput architecture designs for encoding LDPC codes.

Nishil Talati, Zhiying Wang, Shahar Kvatinsky

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Simple magic: Synthesis and in-memory Mapping of logic execution for memristor-aided logic.

Rotem Ben Hur, Nimrod Wald, Nishil Talati, Shahar Kvatinsky

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2015

Stateful-NOR based reconfigurable architecture for logic implementation.

Pravin Mane, Nishil Talati, Ameya Riswadkar, Ramesh Raghu, C. K. Ramesha

Microelectron. J., 2015

Implementation of NOR Logic Based on Material Implication on CMOL FPGA Architecture.

Pravin Mane, Nishil Talati, Ameya Riswadkar, Bhavan Jasani, C. K. Ramesha

Proceedings of the 28th International Conference on VLSI Design, 2015