Nisa Bostanci

According to our database, Nisa Bostanci authored at least 17 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture.

Ataberk Olgun, F. Nisa Bostanci, Geraldo Francisco de Oliveira Junior, Yahya Can Tugrul, Rahul Bera, Abdullah Giray Yaglikçi, Hasan Hassan, Oguz Ergin, Onur Mutlu

ACM Trans. Archit. Code Optim., September, 2024

Amplifying Main Memory-Based Timing Covert and Side Channels using Processing-in-Memory Operations.

Konstantinos Kanellopoulos, F. Nisa Bostanci, Ataberk Olgun, Abdullah Giray Yaglikçi, Ismail Emir Yuksel, Nika Mansouri-Ghiasi, Zülal Bingöl, Mohammad Sadrosadati, Onur Mutlu

CoRR, 2024

MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing.

Geraldo F. Oliveira, Ataberk Olgun, Abdullah Giray Yaglikçi, F. Nisa Bostanci, Juan Gómez-Luna, Saugata Ghose, Onur Mutlu

CoRR, 2024

Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator.

Haocong Luo, Yahya Can Tugrul, F. Nisa Bostanci, Ataberk Olgun, Abdullah Giray Yaglikçi, Onur Mutlu

IEEE Comput. Archit. Lett., 2024

ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation.

Ataberk Olgun, Yahya Can Tugrul, Nisa Bostanci, Ismail Emir Yuksel, Haocong Luo, Steve Rhyner, Abdullah Giray Yaglikçi, Geraldo F. Oliveira, Onur Mutlu

Proceedings of the 33rd USENIX Security Symposium, 2024

Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis.

Ismail Emir Yüksel, Yahya Can Tugrul, Ataberk Olgun, F. Nisa Bostanci, Abdullah Giray Yaglikçi, Geraldo F. Oliveira, Haocong Luo, Juan Gómez-Luna, Mohammad Sadrosadati, Onur Mutlu

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing.

Geraldo F. Oliveira, Ataberk Olgun, Abdullah Giray Yaglikçi, F. Nisa Bostanci, Juan Gómez-Luna, Saugata Ghose, Onur Mutlu

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost.

F. Nisa Bostanci, Ismail Emir Yüksel, Ataberk Olgun, Konstantinos Kanellopoulos, Yahya Can Tugrul, A. Giray Yaglikçi, Mohammad Sadrosadati, Onur Mutlu

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis.

Ismail Emir Yüksel, Yahya Can Tugrul, F. Nisa Bostanci, Geraldo F. Oliveira, A. Giray Yaglikçi, Ataberk Olgun, Melina Soysal, Haocong Luo, Juan Gómez-Luna, Mohammad Sadrosadati, Onur Mutlu

Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2024

2023

PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips.

Ismail Emir Yuksel, Yahya Can Tugrul, F. Nisa Bostanci, Abdullah Giray Yaglikçi, Ataberk Olgun, Geraldo F. Oliveira, Melina Soysal, Haocong Luo, Juan Gómez-Luna, Mohammad Sadrosadati, Onur Mutlu

CoRR, 2023

Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources.

Konstantinos Kanellopoulos, Hong Chul Nam, Nisa Bostanci, Rahul Bera, Mohammad Sadrosadati, Rakesh Kumar, Davide Basilio Bartolini, Onur Mutlu

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings.

Konstantinos Kanellopoulos, Rahul Bera, Kosta Stojiljkovic, F. Nisa Bostanci, Can Firtina, Rachata Ausavarungnirun, Rakesh Kumar, Nastaran Hajinazar, Mohammad Sadrosadati, Nandita Vijaykumar, Onur Mutlu

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

2022

MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations.

Nandita Vijaykumar, Ataberk Olgun, Konstantinos Kanellopoulos, F. Nisa Bostanci, Hasan Hassan, Mehrshad Lotfi, Phillip B. Gibbons, Onur Mutlu

ACM Trans. Archit. Code Optim., 2022

TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs.

Ismail Emir Yüksel, Ataberk Olgun, Behzad Salami, F. Nisa Bostanci, Yahya Can Tugrul, Abdullah Giray Yaglikçi, Nika Mansouri-Ghiasi, Onur Mutlu, Oguz Ergin

CoRR, 2022

Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture.

Ataberk Olgun, F. Nisa Bostanci, Geraldo F. Oliveira, Yahya Can Tugrul, Rahul Bera, Abdullah Giray Yaglikçi, Hasan Hassan, Oguz Ergin, Onur Mutlu

CoRR, 2022

DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators.

F. Nisa Bostanci, Ataberk Olgun, Lois Orosa, Abdullah Giray Yaglikçi, Jeremie S. Kim, Hasan Hassan, Oguz Ergin, Onur Mutlu

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021

QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips.

Ataberk Olgun, Minesh Patel, Abdullah Giray Yaglikçi, Haocong Luo, Jeremie S. Kim, Nisa Bostanci, Nandita Vijaykumar, Oguz Ergin, Onur Mutlu

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021