Nirnjan M. Devashrayee

Orcid: 0000-0001-8161-1361

According to our database1, Nirnjan M. Devashrayee authored at least 14 papers between 2009 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Bibliography

2018
Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator.
Microelectron. J., 2018

2015
Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technology.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2011
Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method.
VLSI Design, 2011

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey.
VLSI Design, 2011

A novel OTA and FVF based second generation current conveyor.
Proceedings of the ICWET '11 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 25, 2011

2010
Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds? - A Survey.
VLSI Design, 2010

Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead.
J. Electron. Test., 2010

Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area Overhead.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Low voltage, high folding rate folding amplifier.
Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26, 2010

2009
Survey of Test Data Compression Technique Emphasizing Code Based Schemes.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Low Voltage, Low Power Folding Amplifier for Folding & Interpolating ADC.
Proceedings of the ARTCom 2009, 2009


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