Nirmal R. Saxena

According to our database1, Nirmal R. Saxena authored at least 43 papers between 1986 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Optimizing Large-Scale Fault Injection Experiments through Martingale Hypothesis: A Systematic Approach for Reliability Assessment of Safety-Critical Systems.
Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2024

2022
Characterizing and Mitigating Soft Errors in GPU DRAM.
IEEE Micro, 2022

Error Model (EM) - A New Way of Doing Fault Simulation.
Proceedings of the IEEE International Test Conference, 2022

Runtime Fault Diagnostics for GPU Tensor Cores.
Proceedings of the IEEE International Test Conference, 2022

2020
On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors.
Proceedings of the IEEE International Test Conference, 2020

2019
Resiliency of automotive object detection networks on GPU architectures.
Proceedings of the IEEE International Test Conference, 2019

2018
Keynote 1: The road to resilient computing in autonomous driving is paved with redundancy.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Low Overhead Tag Error Mitigation for GPU Architectures.
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2018

2008
How Many Test Patterns are Useless?
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

2004
Efficient Design Diversity Estimation for Combinational Circuits.
IEEE Trans. Computers, 2004

Reconfigurable Architecture for Autonomous Self-Repair.
IEEE Des. Test Comput., 2004

2002
A Design Diversity Metric and Analysis of Redundant Systems.
IEEE Trans. Computers, 2002

2001
Techniques for Estimation of Design Diversity for Combinational Logic Circuits.
Proceedings of the 2001 International Conference on Dependable Systems and Networks (DSN 2001) (formerly: FTCS), 2001

2000
Software-implemented EDAC protection against SEUs.
IEEE Trans. Reliab., 2000

Common-mode failures in redundant VLSI systems: a survey.
IEEE Trans. Reliab., 2000

Dependable Computing and Online Testing in Adaptive and Configurable Systems.
IEEE Des. Test Comput., 2000

Fault Escapes in Duplex Systems.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

An ACS Robotic Control Algorithm with Fault Tolerant Capabilities.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

A Reliable LZ Data Compressor on Reconfigurable Coprocessors.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
Finite state machine synthesis with concurrent error detection.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

A design diversity metric and reliability analysis for redundant systems.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
Dependable adaptive computing systems-the ROAR project.
Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, 1998

1997
Parallel Signatur Analysis Design with Bounds on Aliasing.
IEEE Trans. Computers, 1997

1996
Counting Two-State Transition-Tour Sequences.
IEEE Trans. Computers, 1996

Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995
Fault-Tolerant Features in the HaL Memory Management Unit.
IEEE Trans. Computers, 1995

Floating Point Fault Tolerance with Backward Error Assertions.
IEEE Trans. Computers, 1995

Design Verification of a Super-Scalar RISC Processor.
Proceedings of the Digest of Papers: FTCS-25, 1995

Error Detection and Handling in a Superscalar, Speculative Out-of-Order Execution Processor System.
Proceedings of the Digest of Papers: FTCS-25, 1995

1994
Linear Complexity Assertions for Sorting.
IEEE Trans. Software Eng., 1994

HALSIM - a very fast SPARC V9 behavioral model.
SIGARCH Comput. Archit. News, 1994

1993
Algorithmic Synthesis of High Level Tests for Data Path Designs.
Proceedings of the Digest of Papers: FTCS-23, 1993

Concurrent Error Detection/Correction in the HAL MMU Chip.
Proceedings of the Digest of Papers: FTCS-23, 1993

1992
Simple Bounds on Serial Signature Analysis Aliasing for Random Testing.
IEEE Trans. Computers, 1992

1991
Refined Bounds on Signature Analysis Aliasing for Random Testing.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Bounds on Signature Analysis Aliasing for Random Testing.
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

1990
Analysis of Checksums, Extended-Precision Checksums, and Cyclic Redundancy Checks.
IEEE Trans. Computers, 1990

Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums.
IEEE Trans. Computers, 1990

1989
Arithmetic and galois checksums.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
Syndrome and transition count are uncorrelated.
IEEE Trans. Inf. Theory, 1988

Simultaneous signature and syndrome compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1987
A Unified View of Test Compression Methods.
IEEE Trans. Computers, 1987

1986
Accumulator Compression Testing.
IEEE Trans. Computers, 1986


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