Nimish Shah

Orcid: 0000-0003-3234-0715

According to our database1, Nimish Shah authored at least 30 papers between 2004 and 2023.

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Bibliography

2023
Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023

2022
GraphOpt: Constrained-Optimization-Based Parallelization of Irregular Graphs.
IEEE Trans. Parallel Distributed Syst., 2022

DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm.
IEEE J. Solid State Circuits, 2022

DPU-v2: Energy-efficient execution of irregular directed acyclic graphs.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Discrete Samplers for Approximate Inference in Probabilistic Machine Learning.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021



DPU: DAG Processing Unit for Irregular Graphs with Precision-Scalable Posit Arithmetic in 28nm.
CoRR, 2021

9.4 PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020




Dynamic Complexity Tuning for Hardware-Aware Probabilistic Circuits.
Proceedings of the IoT Streams for Data-Driven Predictive Maintenance and IoT, Edge, and Mobile for Embedded Machine Learning, 2020

Discriminative Bias for Learning Probabilistic Sentential Decision Diagrams.
Proceedings of the Advances in Intelligent Data Analysis XVIII, 2020

Acceleration of probabilistic reasoning through custom processor architecture.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019



Towards Hardware-Aware Tractable Learning of Probabilistic Models.
Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019

On Hardware-Aware Probabilistic Frameworks for Resource Constrained Embedded Applications.
Proceedings of the Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing, 2019

ProbLP: A framework for low-precision probabilistic inference.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network.
IEEE Trans. Neural Networks Learn. Syst., 2018

2012
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip.
Proceedings of the International Symposium on Physical Design, 2012

2009
Facial Features Classification Using the Temporal Correlation Matrix Memory (TCMML).
Proceedings of the First International Conference of Soft Computing and Pattern Recognition, 2009

2007
The Improved Correlation Matrix Memory (CMML).
Proceedings of the International Joint Conference on Neural Networks, 2007

2005
"Rippling: Meta-Level Guidance for Mathematical Reasoning, " by Alan Bundy, David Basin, Dieter Hutter, and Andrew Ireland, Cambridge University Press, 2005.
J. Autom. Reason., 2005

2004
Program Construction: Calculating Implementations from Specifications by R.C. Backhouse, John Wiley & Sons, 2004.
J. Funct. Program., 2004

Knowledge Representation, Reasoning and Declarative Problem Solving by C. Baral, Cambridge University Press, 2003.
J. Funct. Program., 2004


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