Nils Wistoff

According to our database, Nils Wistoff authored at least 14 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation.

Luca Valente, Alessandro Nadalini, Asif Hussain Chiralil Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto, Daniele Palossi, Luca Benini, Davide Rossi

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024

vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems.

Enrico Zelioli, Alessandro Ottaviano, Robert Balas, Nils Wistoff, Angelo Garofalo, Luca Benini

CoRR, 2024

fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores through ISA-Supported Temporal Partitioning.

Nils Wistoff, Gernot Heiser, Luca Benini

CoRR, 2024

Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor.

Riccardo Tedeschi, Luca Valente, Gianmarco Ottavi, Enrico Zelioli, Nils Wistoff, Massimiliano Giacometti, Abdul Basit Sajjad, Luca Benini, Davide Rossi

CoRR, 2024

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.

Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning.

Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Gernot Heiser, Luca Benini

IEEE Trans. Computers, May, 2023

Proving the Absence of Microarchitectural Timing Channels.

Scott Buckley, Robert Sison, Nils Wistoff, Curtis Millar, Toby Murray, Gerwin Klein, Gernot Heiser

CoRR, 2023

AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware.

Marcelo Orenes-Vera, Hyunsung Yun, Nils Wistoff, Gernot Heiser, Luca Benini, David Wentzlaff, Margaret Martonosi

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Towards a RISC-V Open Platform for Next-generation Automotive ECUs.

Luca Cuomo, Claudio Scordino, Alessandro Ottaviano, Nils Wistoff, Robert Balas, Luca Benini, Errico Guidieri, Ida Maria Savino

Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs.

Luca Valente, Asif Veeran, Mattia Sinigaglia, Yvan Tortorella, Alessandro Nadalini, Nils Wistoff, Bruno Sá, Angelo Garofalo, Rafail Psiakis, M. Tolba, Ari Kulmala, Nimisha Limaye, Ozgur Sinanoglu, Sandro Pinto, Daniele Palossi, Luca Benini, Baker Mohammad, Davide Rossi

Proceedings of the 35th IEEE Hot Chips Symposium, 2023

2022

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster.

Michael Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank K. Gürkaynak, Luca Benini

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design.

Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini

Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

2021

Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core.

Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core.

Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser

CoRR, 2020