Nilanjan Mukherjee

Orcid: 0000-0001-6689-7525

Affiliations:
  • Siemens Digital Industries Software, Wilsonville, OR,USA
  • Mentor Graphics Corporation, Wilsonville, OR, USA (former)
  • McGill University, Montreal, QC, Canada (PhD 1996)


According to our database1, Nilanjan Mukherjee authored at least 96 papers between 1995 and 2024.

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Bibliography

2024
The Future of Design for Test and Silicon Lifecycle Management.
IEEE Des. Test, August, 2024

Generation of Two-Cycle Tests for Structurally Similar Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024

X-Tolerant Logic BIST for Automotive Designs using Observation Scan Technology.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
Innovation Practices Track: Silicon Lifecycle Management Challenges and Opportunities.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

2022
LBIST for Automotive ICs With Enhanced Test Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Fast Test Generation for Structurally Similar Circuits.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Test Generation for an Iterative Design Flow with RTL Changes.
Proceedings of the IEEE International Test Conference, 2022

2021
Time and Area Optimized Testing of Automotive ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2021

X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Automotive Test and Reliability.
Proceedings of the IEEE International Test Conference in Asia, 2021

2020
Deterministic Stellar BIST for Automotive ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Effective Design of Layout-Friendly EDT Decompressor.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

X-Tolerant Tunable Compactor for In-System Test.
Proceedings of the IEEE International Test Conference, 2020

Test Sequence-Optimized BIST for Automotive Applications.
Proceedings of the IEEE European Test Symposium, 2020

2019
Logic BIST With Capture-Per-Clock Hybrid Test Points.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Test Time and Area Optimized BrST Scheme for Automotive ICs.
Proceedings of the IEEE International Test Conference, 2019

2018
Hardware Protection via Logic Locking Test Points.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Deterministic Stellar BIST for In-System Automotive Test.
Proceedings of the IEEE International Test Conference, 2018

2017
Embedded Deterministic Test Points.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Full-scan LBIST with capture-per-cycle hybrid test points.
Proceedings of the IEEE International Test Conference, 2017

2016
On New Test Points for Compact Cell-Aware Tests.
IEEE Des. Test, 2016

Digital Testing of ICs for Automotive Applications.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Test point insertion in hybrid test compression/LBIST architectures.
Proceedings of the 2016 IEEE International Test Conference, 2016

Minimal area test points for deterministic patterns.
Proceedings of the 2016 IEEE International Test Conference, 2016

On Test Points Enhancing Hardware Security.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Low-Power Programmable PRPG With Test Compression Capabilities.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Isometric Test Data Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Innovative practices session 11C: Advanced scan methodologies [3 presentations].
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Embedded deterministic test points for compact cell-aware tests.
Proceedings of the 2015 IEEE International Test Conference, 2015

Design for low test pattern counts.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Innovative practices session 1C: Existing/emerging low power techniques.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Isometric test compression with low toggling activity.
Proceedings of the 2014 International Test Conference, 2014

On Using Implied Values in EDT-based Test Compression.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Test Time Reduction in EDT Bandwidth Management for SoC Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

On Deploying Scan Chains for Data Storage in Test Compression Environment.
IEEE Des. Test, 2013

EDT bandwidth management - Practical scenarios for large SoC designs.
Proceedings of the 2013 IEEE International Test Conference, 2013

New test compression scheme based on low power BIST.
Proceedings of the 18th IEEE European Test Symposium, 2013

2012
EDT Bandwidth Management in SoC Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Low power programmable PRPG with enhanced fault coverage gradient.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
BIST-Based Fault Diagnosis for Read-Only Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Ring Generator: An Ultimate Linear Feedback Shift Register.
Computer, 2011

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism.
Proceedings of the 2011 IEEE International Test Conference, 2011

Reduced ATE Interface for High Test Data Compression.
Proceedings of the 16th European Test Symposium, 2011

Fault Diagnosis in Memory BIST Environment with Non-march Tests.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Power Aware Embedded Test.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
High Volume Diagnosis in Memory BIST Based on Compressed Failure Data.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

On Compaction Utilizing Inter and Intra-Correlation of Unknown States.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Low capture power at-speed test in EDT environment.
Proceedings of the 2011 IEEE International Test Conference, 2010

Dynamic channel allocation for higher EDT compression in SoC designs.
Proceedings of the 2011 IEEE International Test Conference, 2010

Low power compression of incompatible test cubes.
Proceedings of the 2011 IEEE International Test Conference, 2010

2009
Highly X-Tolerant Selective Compaction of Test Responses.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Defect Aware to Power Conscious Tests - The New DFT Landscape.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

High-Speed On-Chip Event Counters for Embedded Systems.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Fault diagnosis for embedded read-only memories.
Proceedings of the 2009 IEEE International Test Conference, 2009

Compression based on deterministic vector clustering of incompatible test cubes.
Proceedings of the 2009 IEEE International Test Conference, 2009

2008
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST.
Proceedings of the 2008 IEEE International Test Conference, 2008

High Test Quality in Low Pin Count Applications.
Proceedings of the 2008 IEEE International Test Conference, 2008

Targeting "Zero DPPM" - Can we ever get there?
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis.
IEEE Des. Test Comput., 2007

A RTL Testability Analyzer Based on Logical Virtual Prototyping.
Proceedings of the 16th Asian Test Symposium, 2007

2006
High Performance Dense Ring Generators.
IEEE Trans. Computers, 2006

X-Press Compactor for 1000x Reduction of Test Data.
Proceedings of the 2006 IEEE International Test Conference, 2006

A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops.
Proceedings of the 15th Asian Test Symposium, 2006

2005
Full-speed field programmable memory BIST supporting multi-level looping.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Chasing subtle embedded RAM defects for nanometer technologies.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Full-speed field-programmable memory BIST architecture.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Improving Test Quality Using Test Data Compression.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Achieving High Test Quality with Reduced Pin Count Testing.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Embedded deterministic test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Planar High Performance Ring Generators.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Embedded Test for Low Cost Manufacturing.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Cost of Test - Taking Control.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
Embedded Deterministic Test for Low-Cost Manufacturing.
IEEE Des. Test Comput., 2003

Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002
Synthesis of Scan Chains for Netlist Descriptions at RT-Level.
J. Electron. Test., 2002

On Concurrent Test of Core-Based SOC Design.
J. Electron. Test., 2002

Constraint Driven Pin Mapping for Concurrent SOC Testing.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Embedded Deterministic Test for Low-Cost Manufacturing Test.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
Testing Schemes for FIR Filter Structures.
IEEE Trans. Computers, 2001

On RTL scan design.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1999
Built in self test: a complete test solution for telecommunication systems.
IEEE Commun. Mag., 1999

1998
A BIST scheme for the detection of path-delay faults.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
Design of Testable Multipliers for Fixed-Width Data Paths.
IEEE Trans. Computers, 1997

Parameterizable Testing Scheme for FIR Filters.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1995
Arithmetic built-in self test for high-level synthesis.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

On testable multipliers for fixed-width data path architectures.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Software Accelerated Functional Fault Simulation for Data-Path Architectures.
Proceedings of the 32st Conference on Design Automation, 1995


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