Nikos Anastopoulos

According to our database1, Nikos Anastopoulos authored at least 14 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Forecasting Resource Demand for Dynamic Datacenter Sizing in Telco Infrastructures.
Proceedings of the IEEE International Conference on Big Data, 2023

2014
PLQCD library for Lattice QCD on multi-core machines.
CoRR, 2014

LCA: a memory link and cache-aware co-scheduling approach for CMPs.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2012
An Approach to Parallelize Kruskal's Algorithm Using Helper Threads.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2009
Performance evaluation of the sparse matrix-vector multiplication on modern architectures.
J. Supercomput., 2009

Early experiences on accelerating Dijkstra's algorithm using transactional memory.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Employing Transactional Memory and Helper Threads to Speedup Dijkstra's Algorithm.
Proceedings of the ICPP 2009, 2009

Overlapping computation and communication in SMT clusters with commodity interconnects.
Proceedings of the 2009 IEEE International Conference on Cluster Computing, August 31, 2009

2008
Exploring the performance limits of simultaneous multithreading for memory intensive applications.
J. Supercomput., 2008

Understanding the Performance of Sparse Matrix-Vector Multiplication.
Proceedings of the 16th Euromicro International Conference on Parallel, 2008

Facilitating efficient synchronization of asymmetric threads on hyper-threaded processors.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2006
Exploring the Performance Limits of Simultaneous Multithreading for Scientific Codes.
Proceedings of the 2006 International Conference on Parallel Processing (ICPP 2006), 2006

Exploring the Capacity of a Modern SMT Architecture to Deliver High Scientific Application Performance.
Proceedings of the High Performance Computing and Communications, 2006

2005
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures.
Proceedings of the Advances in Informatics, 2005


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