Nikolaos Kefalas

Orcid: 0000-0002-5500-7301

According to our database1, Nikolaos Kefalas authored at least 9 papers between 2010 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2022
An FPGA implementation of the VESA Display Stream Compression decoder.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2019
Low-memory and high-performance architectures for the CCSDS 122.0-B-1 compression standard.
Integr., 2019

Implementing VESA Display Stream Compression Encoder in FPGAs.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

2018
A High Performance Bitplane Encoder for the CCSDS 122.0-B-1 Compression Standard.
Proceedings of the 41st International Conference on Telecommunications and Signal Processing, 2018

2017
High-throughput FPGA implementation of the CCSDS 122.0-B-1 compression standard.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2015
A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter.
Integr., 2015

A parallel luma-chroma filtering architecture for H.264/AVC deblocking filter.
Proceedings of the IEEE 5th International Conference on Consumer Electronics - Berlin, 2015

2014
An 8K-UHD capable 8-stage pipeline deblocking filter for H.264/AVC.
Proceedings of the 6th International Symposium on Communications, 2014

2010
A high throughput pipelined architecture for H.264/AVC deblocking filter.
Proceedings of the 17th IEEE International Conference on Electronics, 2010


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