Nikolaos Ioannis Deligiannis

Orcid: 0000-0002-7948-3361

According to our database1, Nikolaos Ioannis Deligiannis authored at least 17 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Fault Grading Techniques for Evaluating Software-Based Self-Test with Respect to Small Delay Defects.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

Evaluating the Reliability of Integer Multipliers With Respect to Permanent Faults.
Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

2023
Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Automating the Generation of Programs Maximizing the Sustained Switching Activity in Microprocessor units via Evolutionary Techniques.
Microprocess. Microsystems, April, 2023

Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters.
Proceedings of the High Performance Computing, 2023

Constraint-Based Automatic SBST Generation for RISC-V Processor Families.
Proceedings of the IEEE European Test Symposium, 2023

Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing.
Proceedings of the IEEE European Test Symposium, 2023


Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022
Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms.
Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022

Using Formal Methods to Support the Development of STLs for GPUs.
Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021
Towards the Integration of Reliability and Security Mechanisms to Enhance the Fault Resilience of Neural Networks.
IEEE Access, 2021

New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor.
Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020
Evaluating the Code Encryption Effects on Memory Fault Resilience.
Proceedings of the IEEE Latin-American Test Symposium, 2020

Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020


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