Nijwm Wary

Orcid: 0000-0003-4363-7303

According to our database1, Nijwm Wary authored at least 20 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
Energy Efficient Integrated Summer and Latch-Based DFE With Reduced Tap Loading.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
A High-Speed Charge-Injection based Double Tail Latch for Decision Feedback Equalizer (DFE).
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A Fully Integrated SCC DC-DC Converter with Novel FMC Controller for Fast Transient Response.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A 26 Gb/s Echo-Cancellation Based Simultaneous Bidirectional Transceiver in 65 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Current-integrating summer for DFE receiver with low common mode variation.
Microelectron. J., 2022

Fuzzy VIKOR approach to identify COVID-19 vulnerability region to control third wave in Assam, India.
J. Intell. Fuzzy Syst., 2022

Design and Analysis of PVT Invariant Current Reference in 65-nm CMOS.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A Study on Some Properties of Neutrosophic Multi Topological Group.
Symmetry, 2021

A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s.
IEEE Open J. Circuits Syst., 2021

2020
Hybrid bidirectional transceiver for multipoint-to-multipoint signalling across on-chip global interconnects.
IET Circuits Devices Syst., 2020

Discrete Multitone Signalling for Wireline Communication.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

A Regulated-Cascode Based Current-Integrating TIA RX with 1-tap Speculative Adaptive DFE.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2017
Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects.
IEEE J. Solid State Circuits, 2017

2015
High-speed energy-efficient bi-directional transceiver for on-chip global interconnects.
IET Circuits Devices Syst., 2015


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