Nihar R. Mohapatra
Orcid: 0000-0002-8827-5417
According to our database1,
Nihar R. Mohapatra
authored at least 28 papers
between 2001 and 2024.
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Bibliography
2024
Microelectron. J., 2024
K-means Clustering with ANN based Classification to Predict Current-Voltage Characteristics of Advanced FETs.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
A Programmable and Adaptive Dead-Time Controller for Low-Offset Output Generation for Cryo-Cooler Drive Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
Process Voltage Temperature Variability Estimation of Tunneling Current for Band-to-Band-Tunneling based Neuron.
CoRR, 2023
Sub-nanosecond Delay High Voltage Level Shifter in 0.18μm HV-CMOS Technology for Cryo-Cooler Electronics.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
High Resolution Temperature Sensor Signal Processing ASIC for Cryo-Cooler Electronics.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
2021
Behavior of LDMOS transistors at cryogenic temperature - An experiment based analysis.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
The Design of Ultra Low Power SAR ADC for Implantable Cardioverter Defibrillator (ICD).
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
An Ultra Energy Efficient Neuron enabled by Tunneling in Sub-threshold Regime on a Highly Manufacturable 32 nm SOI CMOS Technology.
Proceedings of the 76th Device Research Conference, 2018
2017
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
Trap-assisted carrier transport through the multi-stack gate dielectrics of HKMG nMOS transistors: A compact model.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
2016
Analysis and Modeling of Stress over Layer Induced Threshold Voltage Shift in HKMG nMOS Transistors.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
2003
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
2001
Microelectron. Reliab., 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001