Nidhi Anantharajaiah

Orcid: 0000-0001-7586-0070

According to our database1, Nidhi Anantharajaiah authored at least 13 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Reinforcement Learning Enabled Multi-Layered NoC for Mixed Criticality Systems.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

DREAM: Distributed Reinforcement Learning Enabled Adaptive Mixed-Critical NoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Non-Intrusive Runtime Monitoring for Manycore Prototypes.
Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 2023

LETSCOPE: Lifecycle Extensions Through Software-Defined Predictive Control of Power Electronics.
Proceedings of the 20th IEEE International Conference on Smart Technologies, 2023

2022
The impact of formulation of cost function in Task Mapping Problem on NoCs using bio-inspired based-metaheuristics.
Microprocess. Microsystems, October, 2022

Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality Systems.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021
Ant Colony Optimization Based NoCs for Flexible Spatial Isolation in Mixed Criticality Systems.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

Multi-layered NoCs with Adaptive Routing for Mixed Criticality Systems.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

2020
A Study of the Impact of Formulation of Cost Function in Task Mapping Problem on NoCs.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

2019
A Network on Chip Adapter for Real-Time and Safety-Critical Applications.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Dynamic and scalable runtime block-based multicast routing for networks on chips.
Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

2018
In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

2016
Computational architectures for sonar array processing in autonomous rovers.
Microprocess. Microsystems, 2016


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