Nicolas Gerlin

According to our database1, Nicolas Gerlin authored at least 10 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Special Session: A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

2023
Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Bits, Flips and RISCs.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022
MetFI: Model-driven Fault Simulation Framework.
CoRR, 2022

Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

MetaFS: Model-driven Fault Simulation Framework.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021
Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021


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