Nicolas Bohm Agostini

Orcid: 0000-0003-1855-3810

According to our database1, Nicolas Bohm Agostini authored at least 31 papers between 2019 and 2025.

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Bibliography

2025
Analyzing inference workloads for spatiotemporal modeling.
Future Gener. Comput. Syst., 2025

2024
Data Transfer Optimizations for Host-CPU and Accelerators in AXI4MLIR.
CoRR, 2024

NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2024

Towards Automated Generation of Chiplet-Based Systems Invited Paper.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
SECDA-TFLite: A toolkit for efficient development of FPGA-based DNN accelerators for edge inference.
J. Parallel Distributed Comput., March, 2023

ML-CGRA: An Integrated Compilation Framework to Enable Efficient Machine Learning Acceleration on CGRAs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
VCSR: An Efficient GPU Memory-Aware Sparse Format.
IEEE Trans. Parallel Distributed Syst., 2022

End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators.
IEEE Trans. Computers, 2022

Bridging Python to Silicon: The SODA Toolchain.
IEEE Micro, 2022

SODA Synthesizer: An Open-Source, Multi-Level, Modular, Extensible Compiler from High-Level Frameworks to Silicon.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

DRIPS: Dynamic Rebalancing of Pipelined Streaming Applications on CGRAs.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

From High-Level Frameworks to custom Silicon with SODA.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022

SO(DA)<sup>2</sup>: End-to-end Generation of Specialized Reconfigurable Architectures (Invited Talk).
Proceedings of the 13th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 11th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2022

The SODA approach: leveraging high-level synthesis for hardware/software co-design and hardware specialization: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Hardware acceleration of complex machine learning models through modern high-level synthesis.
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

SODA-OPT an MLIR based flow for co-design and high-level synthesis.
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

2021
Spartan: A Sparsity-Adaptive Framework to Accelerate Deep Neural Network Training on GPUs.
IEEE Trans. Parallel Distributed Syst., 2021

Performance Evaluation and Improvement of Real-Time Computer Vision Applications for Edge Computing Devices.
Proceedings of the ICPE '21: ACM/SPEC International Conference on Performance Engineering, 2021

SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference.
Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurable Array for Streaming Applications.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

A Secure and Reusable Software Architecture for Supporting Online Data Harmonization.
Proceedings of the 2021 IEEE International Conference on Big Data (Big Data), 2021

Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020
Design Space Exploration of Accelerators and End-to-End DNN Evaluation with TFLITE-SOC.
Proceedings of the 32nd IEEE International Symposium on Computer Architecture and High Performance Computing, 2020

2019
Summarizing CPU and GPU Design Trends with Product Data.
CoRR, 2019

Exploiting Adaptive Data Compression to Improve Performance and Energy-Efficiency of Compute Workloads in Multi-GPU Systems.
Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019

Discovering Programmer Intention Behind Written Source Code.
Proceedings of the 18th IEEE International Conference On Machine Learning And Applications, 2019


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