Nicola Nicolici

IEEE Trans. Very Large Scale Integr. Syst., November, 2024

Interview With Vishwani Agrawal.

[BibT_eX]

[DOI]

IEEE Des. Test, October, 2024

Interview With Janusz Rajski.

[BibT_eX]

[DOI]

IEEE Des. Test, August, 2024

Fast Inner-Product Algorithms and Architectures for Deep Neural Network Accelerators.

[BibT_eX]

[DOI]

Trevor E. Pogue

IEEE Trans. Computers, February, 2024

2023

Interview With Prof. Sung-Mo (Steve) Kang.

[BibT_eX]

[DOI]

IEEE Des. Test, June, 2023

Interview With Janet Olson.

[BibT_eX]

[DOI]

IEEE Des. Test, February, 2023

2020

Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault Attacks.

[BibT_eX]

[DOI]

Trevor E. Pogue

IEEE Trans. Very Large Scale Integr. Syst., 2020

2018

Bit-Flip Detection-Driven Selection of Trace Signals.

[BibT_eX]

[DOI]

Amin Vali

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

A generic embedded sequence generator for constrained-random validation with weighted distributions.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

An automated SAT-based method for the design of on-chip bit-flip detectors.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Guest Editors' Introduction: Top Papers from the 2015 International Test Conference.

[BibT_eX]

[DOI]

Haralampos-G. D. Stratigopoulos

IEEE Des. Test, 2016

2015

Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug.

[BibT_eX]

[DOI]

Amin Vali

Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

Emulation-based selection and assessment of assertion checkers for post-silicon validation.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

SAT Solving using FPGA-based Heterogeneous Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A methodology for automated design of embedded bit-flips detectors in post-silicon validation.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

A Multiple-FPGA parallel computing architecture for real-time simulation of soft-object deformation.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

On-chip constrained random stimuli generation for post-silicon validation using compact masks.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging.

[BibT_eX]

[DOI]

Phillip Kinsman

IEEE Trans. Computers, 2013

FPGA acceleration of enhanced boolean constraint propagation for SAT solvers.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment.

[BibT_eX]

[DOI]

Yu-Shen Yang

Andreas G. Veneris

IEEE Trans. Very Large Scale Integr. Syst., 2012

On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

In-system constrained-random stimuli generation for post-silicon validation.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

On-chip stimuli generation for post-silicon validation.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Automated data analysis techniques for a modern silicon debug environment.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Design-for-Debug Architecture for Distributed Embedded Logic Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

An Optimal and Practical Approach to Single Constant Multiplication.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Automated Range and Precision Bit-Width Allocation for Iterative Computations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Trade-Offs in Test Data Compression and Deterministic X-Masking of Responses.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

On Using Lossy Compression for Repeatable Experiments during Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research.

[BibT_eX]

[DOI]

George A. Constantinides

IEEE Des. Test Comput., 2011

Numerical Data Representations for FPGA-Based Scientific Computing.

[BibT_eX]

[DOI]

George A. Constantinides

IEEE Des. Test Comput., 2011

In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A New Algorithm for Post-Silicon Clock Measurement and Tuning.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Dynamic binary translation to a reconfigurable target for on-the-fly acceleration.

[BibT_eX]

[DOI]

Phillip Kinsman

Proceedings of the 48th Design Automation Conference, 2011

2010

Time-Multiplexed Compressed Test of SOC Designs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

A Parallel Computing Platform for Real-Time Haptic Interaction with Deformable Bodies.

[BibT_eX]

[DOI]

IEEE Trans. Haptics, 2010

Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

On improving real-time observability for in-system post-silicon debug.

[BibT_eX]

[DOI]

Proceedings of the 11th Latin American Test Workshop, 2010

Automated trace signals selection using the RTL descriptions.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Automated silicon debug data analysis techniques for a hardware data acquisition environment.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Combined optimal and heuristic approaches for multiple constant multiplication.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

A novel optimal single constant multiplication algorithm.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Post-silicon validation opportunities, challenges and recent advances.

[BibT_eX]

[DOI]

Subhasish Mitra

Sanjit A. Seshia

Proceedings of the 47th Design Automation Conference, 2010

Robust design methods for hardware accelerators for iterative algorithms in scientific computing.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Embedded memory binding in FPGAs.

[BibT_eX]

[DOI]

Kaveh Elizeh

Proceedings of the 47th Design Automation Conference, 2010

2009

Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Real-Time Lossless Compression for Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Computational bit-width allocation for operations in vector calculus.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

Design-for-debug for post-silicon validation: Can high-level descriptions help?

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Resource-Efficient Programmable Trigger Units for Post-Silicon Validation.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE European Test Symposium, 2009

Automated data analysis solutions to silicon debug.

[BibT_eX]

[DOI]

Yu-Shen Yang

Andreas G. Veneris

Proceedings of the Design, Automation and Test in Europe, 2009

Finite Precision bit-width allocation using SAT-Modulo Theory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Guest Editorial.

[BibT_eX]

[DOI]

Patrick Girard

J. Electron. Test., 2008

Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Hardware-based parallel computing for real-time haptic rendering of deformable objects.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2008

On Bypassing Blocking Bugs during Post-Silicon Validation.

[BibT_eX]

[DOI]

Proceedings of the 13th European Test Symposium, 2008

On Automated Trigger Event Generation in Post-Silicon Validation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Power-Aware Testing and Test Strategies for Low Power Devices.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Editorial Silicon Debug and Diagnosis.

[BibT_eX]

[DOI]

Erik Jan Marinissen

IET Comput. Digit. Tech., 2007

DATE 07 workshop on diagnostic services in NoCs.

[BibT_eX]

[DOI]

Erik Jan Marinissen

Axel Jantsch

IEEE Des. Test Comput., 2007

On using lossless compression of debug data in embedded logic analysis.

[BibT_eX]

[DOI]

Ehab Anis

Proceedings of the 2007 IEEE International Test Conference, 2007

Embedded Tutorial on Low Power Test.

[BibT_eX]

[DOI]

Xiaoqing Wen

Proceedings of the 12th European Test Symposium, 2007

Interactive presentation: Low cost debug architecture using lossy compression for silicon debug.

[BibT_eX]

[DOI]

Ehab Anis

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison.

[BibT_eX]

[DOI]

Scott Ollivierre

IEEE Trans. Very Large Scale Integr. Syst., 2006

Multifrequency TAM design for hierarchical SOCs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

RTL Scan Design for Skewed-Load At-speed Test under Power Constraints.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005

Modular and rapid testing of SOCs with unwrapped logic blocks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Wrapper design for multifrequency IP cores.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Synchronization overhead in SOC compressed test.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Modular SOC testing with reduced wrapper count.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

On concurrent test of wrapped cores and unwrapped logic blocks in SOCs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

Multi-frequency wrapper design and optimization for embedded cores under average power constraints.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Proceedings of the 42nd Design Automation Conference, 2005

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Testability Trade-Offs for BIST Data Paths.

[BibT_eX]

[DOI]

J. Electron. Test., 2004

Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Compressed Embedded Diagnosis of Logic Cores.

[BibT_eX]

[DOI]

Scott Ollivierre

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Functional Illinois Scan Design at RTL.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Wrapper Design for Testing IP Cores with Multiple Clock Domains.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Multi-Frequency Test Access Mechanism Design for Modular SOC Testing.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Addressing useless test data in core-based system-on-a-chip test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Variable-length input Huffman coding for system-on-a-chip test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Power-Conscious Test Synthesis and Scheduling.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

On Reducing Wrapper Boundary Register Cells in Modular SOC Testing.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Hardware/Software Co-testing of Embedded Memories in Complex SOCs.

[BibT_eX]

[DOI]

Bai Hong Fang

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Embedded Compact Deterministic Test for IP-Protected Cores.

[BibT_eX]

[DOI]

Jonathan I. Hewitt

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Power-Constrained Embedded Memory BIST Architecture.

[BibT_eX]

[DOI]

Bai Hong Fang

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Delay Fault Testing of Core-Based Systems-on-a-Chi.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Test Data Compression: The System Integrator's Perspective.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

Power profile manipulation: a new approach for reducing test application time under power constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2002

Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Scan Architecture for Shift and Capture Cycle Power Reduction.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Power constrained test scheduling using power profile manipulation.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Testability trade-offs for BIST RTL data paths: the case for three dimensional design space.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

BIST hardware synthesis for RTL data paths based on testcompatibility classes.

[BibT_eX]

[DOI]

Alan Christopher Williams

Andrew D. Brown

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Power conscious test synthesis and scheduling for BIST RTL data paths.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

1999

Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

Correction to the Proof of Theorem 2 in "Parallel Signature Analysis Design with Bounds on Aliasing".

[BibT_eX]

[DOI]